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Differential D78716

[AMDGPU] Avoid hard-coded line numbers in error message checks
ClosedPublic

Authored by foad on Apr 23 2020, 7:35 AM.

Details

Reviewers
arsenm
scott.linder
Commits
rG479145a5c2f2: [AMDGPU] Avoid hard-coded line numbers in error message checks
Summary

This makes it easier for us to maintain downstream changes to some of
these tests. NFC.

Diff Detail

Unit TestsFailed

TimeTest
120 mslldb-unit.Host/_/HostTests::Unknown Unit Message ("")

Event Timeline

foad created this revision.Apr 23 2020, 7:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 23 2020, 7:35 AM
Herald added subscribers: llvm-commits, kerbowa, t-tye and 7 others. · View Herald Transcript
Harbormaster failed remote builds in B54397: Diff 259569!Apr 23 2020, 8:38 AM
arsenm accepted this revision.Apr 23 2020, 12:42 PM
This revision is now accepted and ready to land.Apr 23 2020, 12:42 PM
Closed by commit rG479145a5c2f2: [AMDGPU] Avoid hard-coded line numbers in error message checks (authored by foad). · Explain WhyApr 23 2020, 1:35 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 259569

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:27: incorrect register class for field
# CHECK: scratchRSrcReg: '$noreg'
--- ---
name: noreg_rsrc_reg name: noreg_rsrc_reg
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: '$noreg' scratchRSrcReg: '$noreg'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:21: unknown register name 'not_a_register_name'
# CHECK: scratchRSrcReg: '$not_a_register_name'
--- ---
name: invalid_rsrc_reg name: invalid_rsrc_reg
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: '$not_a_register_name' scratchRSrcReg: '$not_a_register_name'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: unknown register name 'not_a_register_name'
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :8:27: incorrect register class for field
# CHECK: frameOffsetReg: '$vgpr0'
--- ---
name: wrong_reg_class_frame_offset_reg name: wrong_reg_class_frame_offset_reg
machineFunctionInfo: machineFunctionInfo:
frameOffsetReg: '$vgpr0' frameOffsetReg: '$vgpr0'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:21: expected a named register
# CHECK: frameOffsetReg: ''
--- ---
name: empty_frame_offset_reg name: empty_frame_offset_reg
machineFunctionInfo: machineFunctionInfo:
frameOffsetReg: '' frameOffsetReg: ''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:21: expected a named register
# CHECK: scratchRSrcReg: ''
--- ---
name: empty_scratch_rsrc_reg name: empty_scratch_rsrc_reg
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: '' scratchRSrcReg: ''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:24: expected a named register
# CHECK: stackPtrOffsetReg: ''
--- ---
name: empty_stack_ptr_offset_reg name: empty_stack_ptr_offset_reg
machineFunctionInfo: machineFunctionInfo:
stackPtrOffsetReg: '' stackPtrOffsetReg: ''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :8:45: incorrect register class for field
# CHECK: scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'
--- ---
name: wrong_reg_class_scratch_rsrc_reg name: wrong_reg_class_scratch_rsrc_reg
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3' scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...

llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :8:30: incorrect register class for field
# CHECK: stackPtrOffsetReg: '$vgpr0'
--- ---
name: wrong_reg_class_stack_ptr_offset_reg name: wrong_reg_class_stack_ptr_offset_reg
machineFunctionInfo: machineFunctionInfo:
stackPtrOffsetReg: '$vgpr0' stackPtrOffsetReg: '$vgpr0'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: | body: |
bb.0: bb.0:
S_ENDPGM S_ENDPGM
... ...