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Differential D78553

[AMDGPU] Simplify definition of VReg and AReg classes. NFC.
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Authored by foad on Apr 21 2020, 3:51 AM.

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arsenm
rampitec
kerbowa
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rG2fa17cdd7ad0: [AMDGPU] Simplify definition of VReg and AReg classes. NFC.

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foad created this revision.Apr 21 2020, 3:51 AM
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Harbormaster failed remote builds in B54080: Diff 258960!Apr 21 2020, 5:22 AM
rampitec accepted this revision.Apr 21 2020, 10:57 AM

LGTM with couple comments.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td
735

Do you mind to add "let GeneratePressureSet = 0" here before submission?

756

You will need to rebase since you have added more classes by now.

This revision is now accepted and ready to land.Apr 21 2020, 10:57 AM
foad marked an inline comment as done.Apr 22 2020, 12:53 AM
foad added inline comments.
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
735

We're already inside a let GeneratePressureSet = 0 in { ... } block.

Closed by commit rG2fa17cdd7ad0: [AMDGPU] Simplify definition of VReg and AReg classes. NFC. (authored by foad). · Explain WhyApr 22 2020, 1:03 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
110 lines

Diff 259196

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Lines
def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add SGPR_1024)> { (add SGPR_1024)> {
let CopyCost = 16; let CopyCost = 16;
let AllocationPriority = 19; let AllocationPriority = 19;
} }
// Register class for all vector registers (VGPRs + Interploation Registers) // Register class for all vector registers (VGPRs + Interploation Registers)
def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 32, class VRegClass<int numRegs, list<ValueType> regTypes, dag regList> :
(add VGPR_64)> { RegisterClass<"AMDGPU", regTypes, 32, regList> {
let Size = 64; let Size = !mul(numRegs, 32);
// Requires n v_mov_b32 to copy
let CopyCost = numRegs;
let AllocationPriority = numRegs;
let Weight = numRegs;
rampitecUnsubmitted
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Do you mind to add "let GeneratePressureSet = 0" here before submission?

rampitec: Do you mind to add "let GeneratePressureSet = 0" here before submission?
foadAuthorUnsubmitted
Done
ReplyInline Actions

We're already inside a let GeneratePressureSet = 0 in { ... } block.

foad: We're already inside a `let GeneratePressureSet = 0 in { ... }` block.
}
def VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4],
(add VGPR_64)>;
def VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>;
def VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, i128], (add VGPR_128)>;
def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
def VReg_256 : VRegClass<8, [v8i32, v8f32], (add VGPR_256)>;
def VReg_512 : VRegClass<16, [v16i32, v16f32], (add VGPR_512)>;
def VReg_1024 : VRegClass<32, [v32i32, v32f32], (add VGPR_1024)>;
class ARegClass<int numRegs, list<ValueType> regTypes, dag regList> :
VRegClass<numRegs, regTypes, regList> {
// Requires n v_accvgpr_write and n v_accvgpr_read to copy + burn 1 vgpr
let CopyCost = !add(numRegs, numRegs, 1);
}
def AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16],
(add AGPR_64)>;
def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>;
def AReg_512 : ARegClass<16, [v16i32, v16f32], (add AGPR_512)>;
rampitecUnsubmitted
Not Done
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You will need to rebase since you have added more classes by now.

rampitec: You will need to rebase since you have added more classes by now.
def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>;
// Requires 2 v_mov_b32 to copy
let CopyCost = 2;
let AllocationPriority = 2;
let Weight = 2;
}
def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96)> {
let Size = 96;
// Requires 3 v_mov_b32 to copy
let CopyCost = 3;
let AllocationPriority = 3;
let Weight = 3;
}
def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64, i128], 32,
(add VGPR_128)> {
let Size = 128;
// Requires 4 v_mov_b32 to copy
let CopyCost = 4;
let AllocationPriority = 4;
let Weight = 4;
}
def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
(add VGPR_160)> {
let Size = 160;
// Requires 5 v_mov_b32 to copy
let CopyCost = 5;
let AllocationPriority = 5;
let Weight = 5;
}
def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
(add VGPR_256)> {
let Size = 256;
let CopyCost = 8;
let AllocationPriority = 6;
let Weight = 8;
}
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add VGPR_512)> {
let Size = 512;
let CopyCost = 16;
let AllocationPriority = 7;
let Weight = 16;
}
def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add VGPR_1024)> {
let Size = 1024;
let CopyCost = 32;
let AllocationPriority = 8;
let Weight = 32;
}
def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32,
(add AGPR_64)> {
let Size = 64;
let CopyCost = 5;
let AllocationPriority = 2;
}
def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
(add AGPR_128)> {
let Size = 128;
// Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr
let CopyCost = 9;
let AllocationPriority = 4;
}
def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add AGPR_512)> {
let Size = 512;
let CopyCost = 33;
let AllocationPriority = 7;
}
def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add AGPR_1024)> {
let Size = 1024;
let CopyCost = 65;
let AllocationPriority = 8;
}
} // End GeneratePressureSet = 0 } // End GeneratePressureSet = 0
// This is not a real register. This is just to have a register to add // This is not a real register. This is just to have a register to add
// to VReg_1 that does not alias any real register that would // to VReg_1 that does not alias any real register that would
// introduce inferred register classess. // introduce inferred register classess.
def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> { def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> {
let isArtificial = 1; let isArtificial = 1;
} }
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