[AArch64] Clean up assorted usage of hasOneUse/use_instructions [8/10]

[vsk]

Summary

Use the variants of these APIs which skip over debug instructions. This
is mostly a cleanup, but it does fix a debug-variance issue which causes
addsub-shifted.ll and addsub_ext.ll to fail when debug info is inserted
by -mir-debugify.

[aemerson]

LGTM, thanks!

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

 /// Return a register which can be used as a bit to test in a TB(N)Z.
 static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
                               MachineRegisterInfo &MRI) {
   assert(Reg.isValid() && "Expected valid register!");
   while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) {
     unsigned Opc = MI->getOpcode();
 
     if (!MI->getOperand(0).isReg() ||
-        !MRI.hasOneUse(MI->getOperand(0).getReg()))
+        !MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
       break;
 
     // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
     //
     // (tbz (trunc x), b) -> (tbz x, b) is always safe, because the bit number
     // on the truncated x is the same as the bit number on x.
     if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT ||
         Opc == TargetOpcode::G_TRUNC) {
       Register NextReg = MI->getOperand(1).getReg();
       // Did we find something worth folding?
-      if (!NextReg.isValid() || !MRI.hasOneUse(NextReg))
+      if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg))
         break;
 
       // NextReg is worth folding. Keep looking.
       Reg = NextReg;
       continue;
     }
 
     // Attempt to find a suitable operation with a constant on one side.
bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
   // Rather than emitting both of the rather long sequences in the standard
   // G_FCMP/G_SELECT select methods.
 
   // First, check if the condition is defined by a compare.
   MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
   while (CondDef) {
     // We can only fold if all of the defs have one use.
     Register CondDefReg = CondDef->getOperand(0).getReg();
-    if (!MRI.hasOneUse(CondDefReg)) {
+    if (!MRI.hasOneNonDBGUse(CondDefReg)) {
       // Unless it's another select.
-      for (auto UI = MRI.use_instr_begin(CondDefReg), UE = MRI.use_instr_end();
-           UI != UE; ++UI) {
-        if (CondDef == &*UI)
+      for (const MachineInstr &UI : MRI.use_nodbg_instructions(CondDefReg)) {
+        if (CondDef == &UI)
           continue;
-        if (UI->getOpcode() != TargetOpcode::G_SELECT)
+        if (UI.getOpcode() != TargetOpcode::G_SELECT)
           return false;
       }
     }
 
     // We can skip over G_TRUNC since the condition is 1-bit.
     // Truncating/extending can have no impact on the value.
     unsigned Opc = CondDef->getOpcode();
     if (Opc != TargetOpcode::COPY && Opc != TargetOpcode::G_TRUNC)

 
 /// Return true if it is worth folding MI into an extended register. That is,
 /// if it's safe to pull it into the addressing mode of a load or store as a
 /// shift.
 bool AArch64InstructionSelector::isWorthFoldingIntoExtendedReg(
     MachineInstr &MI, const MachineRegisterInfo &MRI) const {
   // Always fold if there is one use, or if we're optimizing for size.
   Register DefReg = MI.getOperand(0).getReg();
-  if (MRI.hasOneUse(DefReg) ||
+  if (MRI.hasOneNonDBGUse(DefReg) ||
       MI.getParent()->getParent()->getFunction().hasMinSize())
     return true;
 
   // It's better to avoid folding and recomputing shifts when we don't have a
   // fastpath.
   if (!STI.hasLSLFast())
     return false;
 
   // We have a fastpath, so folding a shift in and potentially computing it
   // many times may be beneficial. Check if this is only used in memory ops.
   // If it is, then we should fold.
-  return all_of(MRI.use_instructions(DefReg),
+  return all_of(MRI.use_nodbg_instructions(DefReg),
                 [](MachineInstr &Use) { return Use.mayLoadOrStore(); });
 }
 
 InstructionSelector::ComplexRendererFns
 AArch64InstructionSelector::selectExtendedSHL(
     MachineOperand &Root, MachineOperand &Base, MachineOperand &Offset,
     unsigned SizeInBytes, bool WantsExt) const {
   assert(Base.isReg() && "Expected base to be a register operand");
AArch64InstructionSelector::selectAddrModeRegisterOffset(
   // We need a GEP.
   MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
   if (!Gep || Gep->getOpcode() != TargetOpcode::G_PTR_ADD)
     return None;
 
   // If this is used more than once, let's not bother folding.
   // TODO: Check if they are memory ops. If they are, then we can still fold
   // without having to recompute anything.
-  if (!MRI.hasOneUse(Gep->getOperand(0).getReg()))
+  if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg()))
     return None;
 
   // Base is the GEP's LHS, offset is its RHS.
   return {{[=](MachineInstrBuilder &MIB) {
              MIB.addUse(Gep->getOperand(1).getReg());
            },
            [=](MachineInstrBuilder &MIB) {
              MIB.addUse(Gep->getOperand(2).getReg());

llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

case TargetOpcode::G_LOAD:
     // FIXME: Should be derived from the scheduling model.
     if (OpRegBankIdx[0] != PMI_FirstGPR)
       Cost = 2;
     else
       // Check if that load feeds fp instructions.
       // In that case, we want the default mapping to be on FPR
       // instead of blind map every scalar to GPR.
       for (const MachineInstr &UseMI :
-           MRI.use_instructions(MI.getOperand(0).getReg())) {
+           MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
         // If we have at least one direct use in a FP instruction,
         // assume this was a floating point load in the IR.
         // If it was not, we would have had a bitcast before
         // reaching that instruction.
         if (onlyUsesFP(UseMI, MRI, TRI)) {
           OpRegBankIdx[0] = PMI_FirstFPR;
           break;
         }
case TargetOpcode::G_SELECT: {
     unsigned NumFP = 0;
 
     // Check if the uses of the result always produce floating point values.
     //
     // For example:
     //
     // %z = G_SELECT %cond %x %y
     // fpr = G_FOO %z ...
-    if (any_of(
-            MRI.use_instructions(MI.getOperand(0).getReg()),
+    if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))
       ++NumFP;
 
     // Check if the defs of the source values always produce floating point
     // values.
     //
     // For example:
     //
     // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
case TargetOpcode::G_UNMERGE_VALUES: {
     // we preserve that.
     if (OpRegBankIdx[0] != PMI_FirstGPR)
       break;
 
     LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
     // UNMERGE into scalars from a vector should always use FPR.
     // Likewise if any of the uses are FP instructions.
     if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
-        any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
+        any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
       // Set the register bank of every operand to FPR.
       for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
            Idx < NumOperands; ++Idx)
         OpRegBankIdx[Idx] = PMI_FirstFPR;
     }
     break;
   }

llvm/test/CodeGen/AArch64/addsub-shifted.ll

-; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
-; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 -global-isel -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
+; RUN: llc -debugify-and-strip-all-safe -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
+; RUN: llc -debugify-and-strip-all-safe -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 -global-isel -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
 
 ; FALLBACK-NOT: remark
 
 @var32 = global i32 0
 @var64 = global i64 0
 
 define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 ; CHECK-LABEL: test_lsl_arith:

llvm/test/CodeGen/AArch64/addsub_ext.ll

-; RUN: llc -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
-; RUN: llc -global-isel -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s --check-prefix=GISEL
+; RUN: llc -debugify-and-strip-all-safe -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
+; RUN: llc -debugify-and-strip-all-safe -global-isel -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s --check-prefix=GISEL
 
 ; FIXME: GISel only knows how to handle explicit G_SEXT instructions. So when
 ; G_SEXT is lowered to anything else, it won't fold in a stx*.
 ; FIXME: GISel doesn't currently handle folding the addressing mode into a cmp.
 
 @var8 = global i8 0
 @var16 = global i16 0
 @var32 = global i32 0