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GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC
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Authored by arsenm on Apr 4 2020, 1:43 PM.

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Reviewers

aemerson
aditya_nandakumar
dsanders
paquette

Summary

G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector
can also be implemented with a bitcast to a scalar, which introduces
the possibility for infinite loops. Try to eliminate an illegal source
register type in the artifact combiner to avoid this from happening.

Avoids infinite looping in the legalizer in a future patch which
allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.

Diff Detail

Event Timeline

arsenm created this revision.Apr 4 2020, 1:43 PM

Herald added subscribers: kerbowa, rovka, nhaehnle and 2 others. · View Herald TranscriptApr 4 2020, 1:43 PM

arsenm added a child revision: D77476: GlobalISel: Handle more cases in lowerUnmergeValues.Apr 4 2020, 1:51 PM

ping

aemerson added inline comments.Apr 13 2020, 4:36 PM

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
443	How do we make the decision that this the resulting output is "better" than the input? Can we check for input legality or something?

Fix checking wrong instruction opcode, more tests

arsenm marked an inline comment as done.Apr 14 2020, 9:34 AM

arsenm added inline comments.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
443	I don't think anywhere in the artifact combiner is deciding what's really "better". I think what makes most sense is checking if the vector truncate is legal, but that doesn't really work due to the special constraints on G_TRUNC legality. Checking if the unmerge skips cases where it's still beneficial to do the combine, so I'm not sure what else I would do here

arsenm marked an inline comment as done.Apr 14 2020, 9:43 AM

arsenm added inline comments.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
443	I've also been wondering if the conventions of the artifact combiner derive from originally missing most legalization actions on merge/unmerge etc. isInstUnsupported only makes sense to me for poorly defined legalization rules that don't try to handle standalone artifacts as legalizable operations

ping

The description says:

Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening.

I don't see this happening in this patch.

Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2020, 10:57 AM

In D77475#2008333, @aemerson wrote:

The description says:

Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening.

I don't see this happening in this patch.

It eliminates the intermediate illegal vector. In the example in the comment, this is the <4 x s8> vector. It is replaced by doing the unmerge on the original <4 x s32> vector, and inserting scalar G_TRUNCs. Also see my previous question about what "better" really means in the artifact combiner context. Skipping this either or both input operations are already legal blocks this in cases where it still would produce fewer artifacts.

Ok.

This revision is now accepted and ready to land.May 4 2020, 10:16 AM

ee1a69824d9a9fceea2b51616c3363c4d210af4c

Revision Contents

Path

Size

llvm/

include/

llvm/

CodeGen/

GlobalISel/

LegalizationArtifactCombiner.h

36 lines

test/

CodeGen/

AArch64/

GlobalISel/

legalize-select.mir

18 lines

AMDGPU/

GlobalISel/

artifact-combiner-sext.mir

22 lines

artifact-combiner-unmerge-values.mir

321 lines

312 lines

87 lines

48 lines

186 lines

legalize-sext-inreg.mir

130 lines

legalize-trunc.mir

24 lines

legalize-unmerge-values-xfail.mir

legalize-unmerge-values.mir

17 lines

legalize-xor.mir

48 lines

Diff 257380

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 428 Lines • ▼ Show 20 Lines	bool tryCombineMerges(MachineInstr &MI,
// Handle intermediate conversions		// Handle intermediate conversions
unsigned SrcOp = SrcDef->getOpcode();		unsigned SrcOp = SrcDef->getOpcode();
if (isArtifactCast(SrcOp)) {		if (isArtifactCast(SrcOp)) {
ConvertOp = SrcOp;		ConvertOp = SrcOp;
MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI);		MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI);
}		}

if (!MergeI \|\| !canFoldMergeOpcode(MergeI->getOpcode(),		if (!MergeI \|\| !canFoldMergeOpcode(MergeI->getOpcode(),
ConvertOp, OpTy, DestTy))		ConvertOp, OpTy, DestTy)) {
		if (ConvertOp == TargetOpcode::G_TRUNC && OpTy.isVector() &&
		OpTy.getScalarType() == DestTy.getScalarType()) {
		Register TruncSrc = SrcDef->getOperand(1).getReg();
		LLT TruncSrcTy = MRI.getType(TruncSrc);

		// %1:_(<4 x s8>) = G_TRUNC %0(<4 x s32>)
		aemersonUnsubmitted Not Done Reply Inline Actions How do we make the decision that this the resulting output is "better" than the input? Can we check for input legality or something? aemerson: How do we make the decision that this the resulting output is "better" than the input? Can we…
		arsenmAuthorUnsubmitted Done Reply Inline Actions I don't think anywhere in the artifact combiner is deciding what's really "better". I think what makes most sense is checking if the vector truncate is legal, but that doesn't really work due to the special constraints on G_TRUNC legality. Checking if the unmerge skips cases where it's still beneficial to do the combine, so I'm not sure what else I would do here arsenm: I don't think anywhere in the artifact combiner is deciding what's really "better". I think…
		arsenmAuthorUnsubmitted Done Reply Inline Actions I've also been wondering if the conventions of the artifact combiner derive from originally missing most legalization actions on merge/unmerge etc. isInstUnsupported only makes sense to me for poorly defined legalization rules that don't try to handle standalone artifacts as legalizable operations arsenm: I've also been wondering if the conventions of the artifact combiner derive from originally…
		// %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
		// =>
		// %6:_(s32), %7:_(s32), %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %0
		// %2:_(s8) = G_TRUNC %6
		// %3:_(s8) = G_TRUNC %7
		// %4:_(s8) = G_TRUNC %8
		// %5:_(s8) = G_TRUNC %9

		unsigned UnmergeNumElts = DestTy.isVector() ?
		TruncSrcTy.getNumElements() / NumDefs : 1;
		LLT UnmergeTy = TruncSrcTy.changeNumElements(UnmergeNumElts);

		if (isInstUnsupported(
		{TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, TruncSrcTy}}))
return false;		return false;

		Builder.setInstr(MI);
		auto NewUnmerge = Builder.buildUnmerge(UnmergeTy, TruncSrc);

		SmallVector<Register, 8> Regs(NumDefs);
		for (unsigned I = 0; I != NumDefs; ++I)
		Builder.buildTrunc(MI.getOperand(I), NewUnmerge.getReg(I));

		markInstAndDefDead(MI, *SrcDef, DeadInsts);
		return true;
		}

		return false;
		}

const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;		const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;

if (NumMergeRegs < NumDefs) {		if (NumMergeRegs < NumDefs) {
if (NumDefs % NumMergeRegs != 0)		if (NumDefs % NumMergeRegs != 0)
return false;		return false;

Builder.setInstr(MI);		Builder.setInstr(MI);
// Transform to UNMERGEs, for example		// Transform to UNMERGEs, for example
▲ Show 20 Lines • Show All 371 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

Show All 10 Lines	bb.0:

; CHECK-LABEL: name: v2s64		; CHECK-LABEL: name: v2s64
; CHECK: liveins: $q0, $q1		; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1		; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]		; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[ICMP]](<2 x s64>)		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ICMP]](<2 x s64>)
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[TRUNC]](<2 x s1>)		; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s64)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s64)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)		; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UV]](s1), [[UV2]], [[UV4]]		; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[UV2]], [[UV4]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[UV1]](s1), [[UV3]], [[UV5]]		; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[UV3]], [[UV5]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)		; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; CHECK: $q0 = COPY [[BUILD_VECTOR1]](<2 x s64>)		; CHECK: $q0 = COPY [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0		; CHECK: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0		%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1		%1:_(<2 x s64>) = COPY $q1
%3:_(s64) = G_CONSTANT i64 0		%3:_(s64) = G_CONSTANT i64 0
%2:_(<2 x s64>) = G_BUILD_VECTOR %3(s64), %3(s64)		%2:_(<2 x s64>) = G_BUILD_VECTOR %3(s64), %3(s64)
%4:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %2		%4:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %2
Show All 12 Lines	bb.0:

; CHECK-LABEL: name: v2s32		; CHECK-LABEL: name: v2s32
; CHECK: liveins: $d0, $d1		; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1		; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]		; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[ICMP]](<2 x s32>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ICMP]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[TRUNC]](<2 x s1>)		; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s32)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)		; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)		; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[UV]](s1), [[UV2]], [[UV4]]		; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[UV2]], [[UV4]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[UV1]](s1), [[UV3]], [[UV5]]		; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC1]](s1), [[UV3]], [[UV5]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)		; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $d0 = COPY [[BUILD_VECTOR1]](<2 x s32>)		; CHECK: $d0 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0		; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0		%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1		%1:_(<2 x s32>) = COPY $d1
%3:_(s32) = G_CONSTANT i32 0		%3:_(s32) = G_CONSTANT i32 0
%2:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)		%2:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)
%4:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %2		%4:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %2
%5:_(<2 x s32>) = G_SELECT %4(<2 x s1>), %1, %0		%5:_(<2 x s32>) = G_SELECT %4(<2 x s1>), %1, %0
$d0 = COPY %5(<2 x s32>)		$d0 = COPY %5(<2 x s32>)
RET_ReallyLR implicit $d0		RET_ReallyLR implicit $d0

...		...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

	Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1			liveins: $vgpr0_vgpr1

	; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and			; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and
	; unable to legalize. This prevents further legalization.			; unable to legalize. This prevents further legalization.
	; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16			; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
	; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1			; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
	; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
	; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
	; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
	; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8			; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8			; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
	; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535			; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]			; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
	; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]			; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
	; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)			; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
				; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
	; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]			; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
	; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)			; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
	; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)			; CHECK: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
	%0:_(<2 x s32>) = COPY $vgpr0_vgpr1			%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
	%1:_(<2 x s8>) = G_TRUNC %0			%1:_(<2 x s8>) = G_TRUNC %0
	%2:_(<2 x s16>) = G_SEXT %1			%2:_(<2 x s16>) = G_SEXT %1
	$vgpr0 = COPY %2			$vgpr0 = COPY %2
	...			...

	---			---
	name: test_sext_trunc_v3s32_to_v3s16_to_v3s32			name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
	Show All 18 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines

---		---
name: test_unmerge_values_s1_trunc_v4s1_of_concat_vectors_v4s32_v2s32		name: test_unmerge_values_s1_trunc_v4s1_of_concat_vectors_v4s32_v2s32
body: \|		body: \|
bb.0:		bb.0:
; CHECK-LABEL: name: test_unmerge_values_s1_trunc_v4s1_of_concat_vectors_v4s32_v2s32		; CHECK-LABEL: name: test_unmerge_values_s1_trunc_v4s1_of_concat_vectors_v4s32_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3		; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[COPY1]](<2 x s32>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s32>)		; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1), [[UV2:%[0-9]+]]:_(s1), [[UV3:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[TRUNC]](<4 x s1>)		; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)		; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)		; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s1)		; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[UV3]](s1)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: $vgpr0 = COPY [[SEXT]](s32)		; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
; CHECK: $vgpr1 = COPY [[SEXT1]](s32)		; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: $vgpr2 = COPY [[SEXT2]](s32)		; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
; CHECK: $vgpr3 = COPY [[SEXT3]](s32)		; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
		; CHECK: $vgpr1 = COPY [[SEXT_INREG1]](s32)
		; CHECK: $vgpr2 = COPY [[SEXT_INREG2]](s32)
		; CHECK: $vgpr3 = COPY [[SEXT_INREG3]](s32)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1		%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3		%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<4 x s32>) = G_CONCAT_VECTORS %0, %1		%2:_(<4 x s32>) = G_CONCAT_VECTORS %0, %1
%3:_(<4 x s1>) = G_TRUNC %2		%3:_(<4 x s1>) = G_TRUNC %2
%4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1) = G_UNMERGE_VALUES %3		%4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1) = G_UNMERGE_VALUES %3
%8:_(s32) = G_SEXT %4		%8:_(s32) = G_SEXT %4
%9:_(s32) = G_SEXT %5		%9:_(s32) = G_SEXT %5
%10:_(s32) = G_SEXT %6		%10:_(s32) = G_SEXT %6
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines	bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7		; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)		; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)		; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)		; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)		; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[TRUNC3]](s32)		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s32), implicit [[TRUNC1]](s32), implicit [[TRUNC2]](s32), implicit [[TRUNC3]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
; CHECK: S_ENDPGM 0, implicit [[UV4]](s32), implicit [[UV5]](s32), implicit [[UV6]](s32), implicit [[UV7]](s32)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3		%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7		%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<4 x s64>) = G_CONCAT_VECTORS %0, %1		%2:_(<4 x s64>) = G_CONCAT_VECTORS %0, %1
%3:_(<4 x s32>) = G_TRUNC %2		%3:_(<4 x s32>) = G_TRUNC %2
%4:_(s32), %5:_(s32), %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %3		%4:_(s32), %5:_(s32), %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %3
S_ENDPGM 0, implicit %4, implicit %5, implicit %6, implicit %7		S_ENDPGM 0, implicit %4, implicit %5, implicit %6, implicit %7
...		...

▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines	bb.0:
%1:_(<2 x s16>) = COPY $vgpr1		%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1		%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
%3:_(<4 x s32>) = G_ZEXT %2		%3:_(<4 x s32>) = G_ZEXT %2
%4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %3		%4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %3
S_ENDPGM 0, implicit %4, implicit %5		S_ENDPGM 0, implicit %4, implicit %5
...		...

---		---

name: test_unmerge_values_v3s32_of_v12s32_concat_vectors_v4s32		name: test_unmerge_values_v3s32_of_v12s32_concat_vectors_v4s32
body: \|		body: \|
bb.0:		bb.0:
; CHECK-LABEL: name: test_unmerge_values_v3s32_of_v12s32_concat_vectors_v4s32		; CHECK-LABEL: name: test_unmerge_values_v3s32_of_v12s32_concat_vectors_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11		; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>), [[COPY2]](<4 x s32>)		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>), [[COPY2]](<4 x s32>)
▲ Show 20 Lines • Show All 346 Lines • ▼ Show 20 Lines	bb.1:
%31:_(s8) = G_TRUNC %15		%31:_(s8) = G_TRUNC %15
%32:_(<8 x s8>) = G_BUILD_VECTOR %16, %17, %18, %19, %20, %21, %22, %23		%32:_(<8 x s8>) = G_BUILD_VECTOR %16, %17, %18, %19, %20, %21, %22, %23
%33:_(<8 x s8>) = G_BUILD_VECTOR %24, %25, %26, %27, %28, %29, %30, %31		%33:_(<8 x s8>) = G_BUILD_VECTOR %24, %25, %26, %27, %28, %29, %30, %31
%34:_(<16 x s8>) = G_CONCAT_VECTORS %32, %33		%34:_(<16 x s8>) = G_CONCAT_VECTORS %32, %33
%35:_(<16 x s16>) = G_SEXT %34		%35:_(<16 x s16>) = G_SEXT %34
%36:_(<2 x s16>), %37:_(<2 x s16>), %38:_(<2 x s16>), %39:_(<2 x s16>), %40:_(<2 x s16>), %41:_(<2 x s16>), %42:_(<2 x s16>), %43:_(<2 x s16>) = G_UNMERGE_VALUES %35		%36:_(<2 x s16>), %37:_(<2 x s16>), %38:_(<2 x s16>), %39:_(<2 x s16>), %40:_(<2 x s16>), %41:_(<2 x s16>), %42:_(<2 x s16>), %43:_(<2 x s16>) = G_UNMERGE_VALUES %35
S_ENDPGM 0, implicit %36, implicit %37, implicit %38, implicit %39, implicit %40, implicit %41, implicit %42, implicit %43		S_ENDPGM 0, implicit %36, implicit %37, implicit %38, implicit %39, implicit %40, implicit %41, implicit %42, implicit %43
...		...
		---
		name: test_unmerge_values_s8_v4s8_trunc_v4s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_unmerge_values_s8_v4s8_trunc_v4s32
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s8), implicit [[TRUNC1]](s8), implicit [[TRUNC2]](s8), implicit [[TRUNC3]](s8)
		%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<4 x s8>) = G_TRUNC %0
		%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v2s8_v4s8_trunc_v4s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_unmerge_values_v2s8_v4s8_trunc_v4s32
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[UV]](<2 x s32>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[UV1]](<2 x s32>)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](<2 x s8>), implicit [[TRUNC1]](<2 x s8>)
		%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<4 x s8>) = G_TRUNC %0
		%2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_v4s8_v8s8_trunc_v8s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_v4s8_v8s8_trunc_v8s32
		; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[UV]](<4 x s32>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[UV1]](<4 x s32>)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](<4 x s8>), implicit [[TRUNC1]](<4 x s8>)
		%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<8 x s8>) = G_TRUNC %0
		%2:_(<4 x s8>), %3:_(<4 x s8>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_s16_v4s16_trunc_v4s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_unmerge_values_s16_v4s16_trunc_v4s32
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16)
		%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<4 x s16>) = G_TRUNC %0
		%2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v2s16_v4s16_trunc_v4s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_unmerge_values_v2s16_v4s16_trunc_v4s32
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](<2 x s16>), implicit [[TRUNC1]](<2 x s16>)
		%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<4 x s16>) = G_TRUNC %0
		%2:_(<2 x s16>), %3:_(<2 x s16>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_v2s16_v8s16_trunc_v8s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_v2s16_v8s16_trunc_v8s32
		; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>), [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV3]](<2 x s32>)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](<2 x s16>), implicit [[TRUNC1]](<2 x s16>), implicit [[TRUNC2]](<2 x s16>), implicit [[TRUNC3]](<2 x s16>)
		%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<8 x s16>) = G_TRUNC %0
		%2:_(<2 x s16>), %3:_(<2 x s16>), %4:_(<2 x s16>), %5:_(<2 x s16>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v4s16_v8s16_trunc_v8s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_v4s16_v8s16_trunc_v8s32
		; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
		; CHECK: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV]](<4 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV3]](<2 x s32>)
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>)
		; CHECK: [[UV4:%[0-9]+]]:_(<2 x s32>), [[UV5:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV4]](<2 x s32>)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV5]](<2 x s32>)
		; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[TRUNC2]](<2 x s16>), [[TRUNC3]](<2 x s16>)
		; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>), implicit [[CONCAT_VECTORS1]](<4 x s16>)
		%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<8 x s16>) = G_TRUNC %0
		%2:_(<4 x s16>), %3:_(<4 x s16>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_s8_v4s8_trunc_v4s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1

		; CHECK-LABEL: name: test_unmerge_values_s8_v4s8_trunc_v4s16
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
		; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[BITCAST]](s32)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR]](s32)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[BITCAST1]](s32)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR1]](s32)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s8), implicit [[TRUNC1]](s8), implicit [[TRUNC2]](s8), implicit [[TRUNC3]](s8)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s8>) = G_TRUNC %0
		%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v2s8_v4s8_trunc_v4s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1

		; CHECK-LABEL: name: test_unmerge_values_v2s8_v4s8_trunc_v4s16
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[UV]](<2 x s16>)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[UV1]](<2 x s16>)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](<2 x s8>), implicit [[TRUNC1]](<2 x s8>)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s8>) = G_TRUNC %0
		%2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_s32_v4s32_trunc_v4s64
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_s32_v4s32_trunc_v4s64
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s32), implicit [[TRUNC1]](s32), implicit [[TRUNC2]](s32), implicit [[TRUNC3]](s32)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<4 x s32>) = G_TRUNC %0
		%2:_(s32), %3:_(s32), %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v2s32_v4s32_trunc_v4s64
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_v2s32_v4s32_trunc_v4s64
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](<2 x s64>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
		; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](<2 x s64>)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[UV4]](s64)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[UV5]](s64)
		; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC2]](s32), [[TRUNC3]](s32)
		; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>), implicit [[BUILD_VECTOR1]](<2 x s32>)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<4 x s32>) = G_TRUNC %0
		%2:_(<2 x s32>), %3:_(<2 x s32>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

		---
		name: test_unmerge_values_s16_v4s16_trunc_v4s64
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_s16_v4s16_trunc_v4s64
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s64)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s64)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s64)
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s64)
		; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<4 x s16>) = G_TRUNC %0
		%2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3, implicit %4, implicit %5

		...

		---
		name: test_unmerge_values_v2s16_v4s16_trunc_v4s64
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7

		; CHECK-LABEL: name: test_unmerge_values_v2s16_v4s16_trunc_v4s64
		; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](<2 x s64>)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
		; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
		; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
		; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](<2 x s64>)
		; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[UV4]](s64)
		; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
		; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[UV5]](s64)
		; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
		; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
		; CHECK: S_ENDPGM 0, implicit [[BITCAST]](<2 x s16>), implicit [[BITCAST1]](<2 x s16>)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<4 x s16>) = G_TRUNC %0
		%2:_(<2 x s16>), %3:_(<2 x s16>) = G_UNMERGE_VALUES %1
		S_ENDPGM 0, implicit %2, implicit %3

		...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

	Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines

	---			---
	name: test_and_v4s8			name: test_and_v4s8
	body: \|			body: \|
	bb.0:			bb.0:

	; CHECK-LABEL: name: test_and_v4s8			; CHECK-LABEL: name: test_and_v4s8
	; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)			; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
	; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>)			; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
	; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)			; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
	; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)			; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
	; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
	; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)			; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
	; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)			; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
	; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]			; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
	; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)			; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
	; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)			; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
	; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]			; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[AND]](s32)			; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)			; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)			; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)			; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
	; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
	; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
	; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)			; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
	%0:_(<4 x s8>) = G_IMPLICIT_DEF			%0:_(<4 x s8>) = G_IMPLICIT_DEF
	%1:_(<4 x s8>) = G_IMPLICIT_DEF			%1:_(<4 x s8>) = G_IMPLICIT_DEF
	%2:_(<4 x s8>) = G_AND %0, %1			%2:_(<4 x s8>) = G_AND %0, %1
	%3:_(<4 x s32>) = G_ANYEXT %2			%3:_(<4 x s32>) = G_ANYEXT %2
	$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3			$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
	...			...

	---			---
	name: test_and_v8s8			name: test_and_v8s8
	body: \|			body: \|
	bb.0:			bb.0:

	; CHECK-LABEL: name: test_and_v8s8			; CHECK-LABEL: name: test_and_v8s8
	; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[DEF]](<8 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[DEF1]](<8 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<8 x s8>)			; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
	; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<8 x s8>)			; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
	; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)			; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
	; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)			; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
	; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
	; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)			; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
	; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV10]](s8)			; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
	; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]			; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
	; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)			; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
	; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV11]](s8)			; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
	; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]			; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
	; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)			; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
	; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV12]](s8)			; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
	; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[ANYEXT9]]			; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
	; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)			; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
	; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV13]](s8)			; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
	; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT10]], [[ANYEXT11]]			; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
	; CHECK: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)			; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
	; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)			; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
	; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT12]], [[ANYEXT13]]			; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
	; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)			; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
	; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)			; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
	; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT14]], [[ANYEXT15]]			; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[AND]](s32)			; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)			; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)			; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)			; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)			; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)			; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
	; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)			; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
	; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)			; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
	; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
	; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
	; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
	; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)			; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
	; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)			; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
	; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)			; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
	; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)			; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
	; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
	; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)			; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
	%0:_(<8 x s8>) = G_IMPLICIT_DEF			%0:_(<8 x s8>) = G_IMPLICIT_DEF
	%1:_(<8 x s8>) = G_IMPLICIT_DEF			%1:_(<8 x s8>) = G_IMPLICIT_DEF
	%2:_(<8 x s8>) = G_AND %0, %1			%2:_(<8 x s8>) = G_AND %0, %1
	%3:_(<8 x s32>) = G_ANYEXT %2			%3:_(<8 x s32>) = G_ANYEXT %2
	$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %3			$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %3
	...			...

	---			---
	name: test_and_v16s8			name: test_and_v16s8
	body: \|			body: \|
	bb.0:			bb.0:

	; CHECK-LABEL: name: test_and_v16s8			; CHECK-LABEL: name: test_and_v16s8
	; CHECK: [[DEF:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[DEF]](<16 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[DEF1]](<16 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(<8 x s8>), [[UV1:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[TRUNC]](<16 x s8>)			; CHECK: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
	; CHECK: [[UV2:%[0-9]+]]:_(<8 x s8>), [[UV3:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[TRUNC1]](<16 x s8>)			; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<8 x s32>)
	; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV]](<8 x s8>)			; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](<8 x s32>)
	; CHECK: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8), [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV2]](<8 x s8>)			; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
	; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV12]](s8)			; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
	; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
	; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV13]](s8)			; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
	; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
	; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)			; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
	; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)			; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
	; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]			; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
	; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)			; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
	; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)			; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
	; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]			; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
	; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)			; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV16]](s32)
	; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV16]](s8)			; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
	; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[ANYEXT9]]			; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
	; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)			; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
	; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV17]](s8)			; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
	; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT10]], [[ANYEXT11]]			; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
	; CHECK: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[UV10]](s8)			; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV18]](s32)
	; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[UV18]](s8)			; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
	; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT12]], [[ANYEXT13]]			; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
	; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV11]](s8)			; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV19]](s32)
	; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV19]](s8)			; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
	; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT14]], [[ANYEXT15]]			; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[AND]](s32)			; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)			; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)			; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)			; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)			; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)			; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
	; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)			; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
	; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)			; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<8 x s32>)
	; CHECK: [[UV20:%[0-9]+]]:_(s8), [[UV21:%[0-9]+]]:_(s8), [[UV22:%[0-9]+]]:_(s8), [[UV23:%[0-9]+]]:_(s8), [[UV24:%[0-9]+]]:_(s8), [[UV25:%[0-9]+]]:_(s8), [[UV26:%[0-9]+]]:_(s8), [[UV27:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV1]](<8 x s8>)			; CHECK: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](<8 x s32>)
	; CHECK: [[UV28:%[0-9]+]]:_(s8), [[UV29:%[0-9]+]]:_(s8), [[UV30:%[0-9]+]]:_(s8), [[UV31:%[0-9]+]]:_(s8), [[UV32:%[0-9]+]]:_(s8), [[UV33:%[0-9]+]]:_(s8), [[UV34:%[0-9]+]]:_(s8), [[UV35:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV3]](<8 x s8>)			; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[UV20]](s32)
	; CHECK: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[UV20]](s8)			; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV28]](s32)
	; CHECK: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[UV28]](s8)			; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[COPY25]]
	; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT16]], [[ANYEXT17]]			; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV21]](s32)
	; CHECK: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[UV21]](s8)			; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV29]](s32)
	; CHECK: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[UV29]](s8)			; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[COPY27]]
	; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT18]], [[ANYEXT19]]			; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV22]](s32)
	; CHECK: [[ANYEXT20:%[0-9]+]]:_(s32) = G_ANYEXT [[UV22]](s8)			; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV30]](s32)
	; CHECK: [[ANYEXT21:%[0-9]+]]:_(s32) = G_ANYEXT [[UV30]](s8)			; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[COPY29]]
	; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT20]], [[ANYEXT21]]			; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV23]](s32)
	; CHECK: [[ANYEXT22:%[0-9]+]]:_(s32) = G_ANYEXT [[UV23]](s8)			; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[UV31]](s32)
	; CHECK: [[ANYEXT23:%[0-9]+]]:_(s32) = G_ANYEXT [[UV31]](s8)			; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[COPY31]]
	; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT22]], [[ANYEXT23]]			; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[UV24]](s32)
	; CHECK: [[ANYEXT24:%[0-9]+]]:_(s32) = G_ANYEXT [[UV24]](s8)			; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[UV32]](s32)
	; CHECK: [[ANYEXT25:%[0-9]+]]:_(s32) = G_ANYEXT [[UV32]](s8)			; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[COPY33]]
	; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT24]], [[ANYEXT25]]			; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[UV25]](s32)
	; CHECK: [[ANYEXT26:%[0-9]+]]:_(s32) = G_ANYEXT [[UV25]](s8)			; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[UV33]](s32)
	; CHECK: [[ANYEXT27:%[0-9]+]]:_(s32) = G_ANYEXT [[UV33]](s8)			; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[COPY35]]
	; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT26]], [[ANYEXT27]]			; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[UV26]](s32)
	; CHECK: [[ANYEXT28:%[0-9]+]]:_(s32) = G_ANYEXT [[UV26]](s8)			; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
	; CHECK: [[ANYEXT29:%[0-9]+]]:_(s32) = G_ANYEXT [[UV34]](s8)			; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[COPY37]]
	; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT28]], [[ANYEXT29]]			; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[UV27]](s32)
	; CHECK: [[ANYEXT30:%[0-9]+]]:_(s32) = G_ANYEXT [[UV27]](s8)			; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[UV35]](s32)
	; CHECK: [[ANYEXT31:%[0-9]+]]:_(s32) = G_ANYEXT [[UV35]](s8)			; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[COPY39]]
	; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ANYEXT30]], [[ANYEXT31]]			; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
	; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)			; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[AND9]](s32)
	; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND9]](s32)			; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[AND10]](s32)
	; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND10]](s32)			; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)
	; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)			; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[AND12]](s32)
	; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[AND12]](s32)			; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[AND13]](s32)
	; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[AND13]](s32)			; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[AND14]](s32)
	; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[AND14]](s32)			; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[AND15]](s32)
	; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[AND15]](s32)			; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
	; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
	; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
	; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
	; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)			; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
	; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)			; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
	; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)			; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
	; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)			; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
	; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)			; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[COPY40]](s32)
	; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)			; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[COPY41]](s32)
	; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)			; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[COPY42]](s32)
	; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)			; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[COPY43]](s32)
	; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)			; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[COPY44]](s32)
	; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)			; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[COPY45]](s32)
	; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)			; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[COPY46]](s32)
	; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)			; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[COPY47]](s32)
	; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32), [[COPY53]](s32), [[COPY54]](s32), [[COPY55]](s32), [[COPY56]](s32), [[COPY57]](s32), [[COPY58]](s32), [[COPY59]](s32), [[COPY60]](s32), [[COPY61]](s32), [[COPY62]](s32), [[COPY63]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
	; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)			; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
	%0:_(<16 x s8>) = G_IMPLICIT_DEF			%0:_(<16 x s8>) = G_IMPLICIT_DEF
	%1:_(<16 x s8>) = G_IMPLICIT_DEF			%1:_(<16 x s8>) = G_IMPLICIT_DEF
	%2:_(<16 x s8>) = G_AND %0, %1			%2:_(<16 x s8>) = G_AND %0, %1
	%3:_(<16 x s32>) = G_ANYEXT %2			%3:_(<16 x s32>) = G_ANYEXT %2
	$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %3			$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %3
	...			...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

	Show First 20 Lines • Show All 368 Lines • ▼ Show 20 Lines
	---			---
	name: test_bitcast_v3s8_to_s24			name: test_bitcast_v3s8_to_s24
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1_vgpr2			liveins: $vgpr0_vgpr1_vgpr2

	; CHECK-LABEL: name: test_bitcast_v3s8_to_s24			; CHECK-LABEL: name: test_bitcast_v3s8_to_s24
	; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY]](<3 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<3 x s8>)
	; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
	; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[UV]](s8)			; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
	; CHECK: [[ZEXT1:%[0-9]+]]:_(s16) = G_ZEXT [[UV1]](s8)			; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
	; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8			; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
	; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[ZEXT1]], [[C]](s16)			; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
	; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[ZEXT]], [[SHL]]			; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
	; CHECK: [[ZEXT2:%[0-9]+]]:_(s16) = G_ZEXT [[UV2]](s8)			; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
	; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255			; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
	; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)			; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
	; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]			; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
	; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND]], [[C]](s16)			; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
	; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[ZEXT2]], [[SHL1]]			; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
	; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)			; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
	; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)			; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
				; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
				; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
				; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
	; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16			; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
	; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C2]](s32)			; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
	; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT3]], [[SHL2]]			; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
	; CHECK: $vgpr0 = COPY [[COPY1]](s32)			; CHECK: $vgpr0 = COPY [[COPY1]](s32)
	%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	%1:_(<3 x s8>) = G_TRUNC %0			%1:_(<3 x s8>) = G_TRUNC %0
	%2:_(s24) = G_BITCAST %1			%2:_(s24) = G_BITCAST %1
	%3:_(s32) = G_ANYEXT %2			%3:_(s32) = G_ANYEXT %2
	$vgpr0 = COPY %3			$vgpr0 = COPY %3
	...			...

	---			---
	name: test_bitcast_v3s16_to_s48			name: test_bitcast_v3s16_to_s48
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1_vgpr2			liveins: $vgpr0_vgpr1_vgpr2

	; CHECK-LABEL: name: test_bitcast_v3s16_to_s48			; CHECK-LABEL: name: test_bitcast_v3s16_to_s48
	; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
	; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF			; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[DEF]](s32)			; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
	; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR1]](<2 x s32>)			; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF			; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
	; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>), [[DEF1]](<2 x s16>)			; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
	; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
	; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
	; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
	; CHECK: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
	; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
	; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
	; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
	; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
	; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
	; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
	; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
	; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
	; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]			; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
	; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]			; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
	; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0			; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
	; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)			; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
	; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]			; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
	; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)			; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)			; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
	; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)			; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
	%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	%1:_(<3 x s16>) = G_TRUNC %0			%1:_(<3 x s16>) = G_TRUNC %0
	%2:_(s48) = G_BITCAST %1			%2:_(s48) = G_BITCAST %1
	%3:_(s64) = G_ANYEXT %2			%3:_(s64) = G_ANYEXT %2
	Show All 27 Lines
	---			---
	name: test_bitcast_v2s8_to_s16			name: test_bitcast_v2s8_to_s16
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1			liveins: $vgpr0_vgpr1

	; CHECK-LABEL: name: test_bitcast_v2s8_to_s16			; CHECK-LABEL: name: test_bitcast_v2s8_to_s16
	; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1			; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
	; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[COPY]](<2 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<2 x s8>)			; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
	; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[UV]](s8)			; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
	; CHECK: [[ZEXT1:%[0-9]+]]:_(s16) = G_ZEXT [[UV1]](s8)			; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
	; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8			; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
	; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[ZEXT1]], [[C]](s16)			; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
	; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[ZEXT]], [[SHL]]			; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
				; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
				; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)			; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
	; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)			; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
	%0:_(<2 x s32>) = COPY $vgpr0_vgpr1			%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
	%1:_(<2 x s8>) = G_TRUNC %0			%1:_(<2 x s8>) = G_TRUNC %0
	%2:_(s16) = G_BITCAST %1			%2:_(s16) = G_BITCAST %1
	%3:_(s32) = G_ANYEXT %2			%3:_(s32) = G_ANYEXT %2
	$vgpr0 = COPY %3			$vgpr0 = COPY %3
	...			...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

	Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines

	---			---
	name: test_or_v4s8			name: test_or_v4s8
	body: \|			body: \|
	bb.0:			bb.0:

	; CHECK-LABEL: name: test_or_v4s8			; CHECK-LABEL: name: test_or_v4s8
	; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)			; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
	; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>)			; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
	; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)			; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
	; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
	; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)			; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
	; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
	; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)			; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
	; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)			; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
	; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]			; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
	; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)			; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
	; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)			; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
	; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]			; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[OR]](s32)			; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)			; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)			; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)			; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
	; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
	; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
	; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)			; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
	%0:_(<4 x s8>) = G_IMPLICIT_DEF			%0:_(<4 x s8>) = G_IMPLICIT_DEF
	%1:_(<4 x s8>) = G_IMPLICIT_DEF			%1:_(<4 x s8>) = G_IMPLICIT_DEF
	%2:_(<4 x s8>) = G_OR %0, %1			%2:_(<4 x s8>) = G_OR %0, %1
	%3:_(<4 x s32>) = G_ANYEXT %2			%3:_(<4 x s32>) = G_ANYEXT %2
	$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3			$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
	...			...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Lines	body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4		liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4

; CHECK-LABEL: name: test_select_v2s8		; CHECK-LABEL: name: test_select_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2		; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4		; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[COPY1]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[COPY2]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<2 x s8>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<2 x s8>)		; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]		; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]]		; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)		; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)		; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0		%1:_(s32) = G_CONSTANT i32 0
%2:_(<2 x s32>) = COPY $vgpr1_vgpr2		%2:_(<2 x s32>) = COPY $vgpr1_vgpr2
%3:_(<2 x s32>) = COPY $vgpr3_vgpr4		%3:_(<2 x s32>) = COPY $vgpr3_vgpr4
%4:_(<2 x s8>) = G_TRUNC %2		%4:_(<2 x s8>) = G_TRUNC %2
%5:_(<2 x s8>) = G_TRUNC %3		%5:_(<2 x s8>) = G_TRUNC %3
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines	body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8		liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8

; CHECK-LABEL: name: test_select_v4s8		; CHECK-LABEL: name: test_select_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8		; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY1]](<4 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY2]](<4 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>)		; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]		; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]]		; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)		; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)		; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT4]], [[ANYEXT5]]		; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)		; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)		; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT6]], [[ANYEXT7]]		; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC6]], [[TRUNC7]]
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT3]](s16)		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT3]](s16)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)		; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)		; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)		; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)		; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0		%1:_(s32) = G_CONSTANT i32 0
%2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4		%2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8		%3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(<4 x s8>) = G_TRUNC %2		%4:_(<4 x s8>) = G_TRUNC %2
%5:_(<4 x s8>) = G_TRUNC %3		%5:_(<4 x s8>) = G_TRUNC %3
▲ Show 20 Lines • Show All 849 Lines • ▼ Show 20 Lines	bb.0:
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5		; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8		; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11		; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)		; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY2]](<3 x s32>)		; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY3]](<3 x s32>)		; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<3 x s8>)		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<3 x s8>)		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)		; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV9]](s8)		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)		; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV10]](s8)		; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[ANYEXT2]], [[ANYEXT3]]		; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV8]](s8)		; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[TRUNC4]], [[TRUNC5]]
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV11]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[ANYEXT4]], [[ANYEXT5]]		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)		; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)		; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)		; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2		%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5		%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8		%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11		%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1		%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s8>) = G_TRUNC %2		%5:_(<3 x s8>) = G_TRUNC %2
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; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8		; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11		; CHECK: [[COPY3:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)		; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)		; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV6]](s32), [[UV7]](s32)		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV8]](s32), [[DEF]](s32)		; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>), [[DEF1]](<2 x s16>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)		; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<3 x s32>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV9]](s32), [[UV10]](s32)		; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV11]](s32), [[DEF]](s32)		; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR2]](<2 x s32>)		; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR3]](<2 x s32>)		; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC3]]
; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[TRUNC2]](<2 x s16>), [[TRUNC3]](<2 x s16>), [[DEF1]](<2 x s16>)		; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[TRUNC1]], [[TRUNC4]]
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<6 x s16>), 0		; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[TRUNC2]], [[TRUNC5]]
; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0
; CHECK: [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV14]](<2 x s16>)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV15]](<2 x s16>)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC4]], [[TRUNC7]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[TRUNC5]], [[TRUNC8]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP2]](s1), [[TRUNC6]], [[TRUNC9]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)		; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT1]](s16)		; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT1]](s16)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT2]](s16)		; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS2]](<4 x s16>), 0		; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT2]](<3 x s16>), 0		; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)		; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV16]](<2 x s16>)		; CHECK: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)		; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV17]](<2 x s16>)		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)		; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)		; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)		; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR4]](<3 x s32>)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
		; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2		%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5		%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8		%2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11		%3:_(<3 x s32>) = COPY $vgpr9_vgpr10_vgpr11
%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1		%4:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<3 x s16>) = G_TRUNC %2		%5:_(<3 x s16>) = G_TRUNC %2
%6:_(<3 x s16>) = G_TRUNC %3		%6:_(<3 x s16>) = G_TRUNC %3
%7:_(<3 x s16>) = G_SELECT %4, %5, %6		%7:_(<3 x s16>) = G_SELECT %4, %5, %6
%8:_(<3 x s32>) = G_ANYEXT %7		%8:_(<3 x s32>) = G_ANYEXT %7
$vgpr0_vgpr1_vgpr2 = COPY %8		$vgpr0_vgpr1_vgpr2 = COPY %8

...		...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

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; GFX9-LABEL: name: test_sext_inreg_v6s16_1		; GFX9-LABEL: name: test_sext_inreg_v6s16_1
; GFX9: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF		; GFX9: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; GFX9: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>), [[UV2:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)		; GFX9: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>), [[UV2:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; GFX9: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)		; GFX9: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)
; GFX9: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)		; GFX9: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)		; GFX9: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>), [[TRUNC2]](<2 x s16>)
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15		; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[C]](s32)		; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[C]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[UV3]], [[BUILD_VECTOR_TRUNC]](<2 x s16>)		; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC]], [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR_TRUNC]](<2 x s16>)		; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)		; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[UV4]], [[BUILD_VECTOR_TRUNC1]](<2 x s16>)		; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC1]], [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL1]], [[BUILD_VECTOR_TRUNC1]](<2 x s16>)		; GFX9: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL1]], [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)		; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(<2 x s16>) = G_SHL [[UV5]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)		; GFX9: [[SHL2:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC2]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[ASHR2:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL2]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)		; GFX9: [[ASHR2:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL2]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ASHR]](<2 x s16>), [[ASHR1]](<2 x s16>), [[ASHR2]](<2 x s16>)		; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ASHR]](<2 x s16>), [[ASHR1]](<2 x s16>), [[ASHR2]](<2 x s16>)
; GFX9: S_ENDPGM 0, implicit [[CONCAT_VECTORS1]](<6 x s16>)		; GFX9: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
; GFX8-LABEL: name: test_sext_inreg_v6s16_1		; GFX8-LABEL: name: test_sext_inreg_v6s16_1
; GFX8: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF		; GFX8: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; GFX8: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>), [[UV2:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)		; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; GFX8: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; GFX8: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)		; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)		; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)		; GFX8: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; GFX8: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC1]](<2 x s16>)		; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)		; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX8: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)		; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C]](s16)
; GFX8: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC2]](<2 x s16>)		; GFX8: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[SHL2]], [[C]](s16)
; GFX8: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)		; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C]](s16)
; GFX8: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX8: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[SHL3]], [[C]](s16)
; GFX8: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)		; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[TRUNC4]], [[C]](s16)
; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 15		; GFX8: [[ASHR4:%[0-9]+]]:_(s16) = G_ASHR [[SHL4]], [[C]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C1]](s16)		; GFX8: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[TRUNC5]], [[C]](s16)
; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)		; GFX8: [[ASHR5:%[0-9]+]]:_(s16) = G_ASHR [[SHL5]], [[C]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC4]], [[C1]](s16)
; GFX8: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C1]](s16)
; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC5]], [[C1]](s16)
; GFX8: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[SHL2]], [[C1]](s16)
; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC6]], [[C1]](s16)
; GFX8: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[SHL3]], [[C1]](s16)
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[TRUNC7]], [[C1]](s16)
; GFX8: [[ASHR4:%[0-9]+]]:_(s16) = G_ASHR [[SHL4]], [[C1]](s16)
; GFX8: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[TRUNC8]], [[C1]](s16)
; GFX8: [[ASHR5:%[0-9]+]]:_(s16) = G_ASHR [[SHL5]], [[C1]](s16)
; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR]](s16)		; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR]](s16)
; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR1]](s16)		; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR1]](s16)
; GFX8: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)		; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; GFX8: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]		; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
; GFX8: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR2]](s16)		; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR2]](s16)
; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR3]](s16)		; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR3]](s16)
; GFX8: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)		; GFX8: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL7]]		; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL7]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR4]](s16)		; GFX8: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR4]](s16)
; GFX8: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR5]](s16)		; GFX8: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR5]](s16)
; GFX8: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C]](s32)		; GFX8: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C1]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL8]]		; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL8]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)		; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX8: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
; GFX8: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)		; GFX8: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
; GFX6-LABEL: name: test_sext_inreg_v6s16_1		; GFX6-LABEL: name: test_sext_inreg_v6s16_1
; GFX6: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF		; GFX6: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; GFX6: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>), [[UV2:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)		; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; GFX6: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV]](<2 x s32>)		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV1]](<2 x s32>)
; GFX6: [[TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[UV2]](<2 x s32>)
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1		; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1		; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)		; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]		; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)		; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
; GFX6: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)		; GFX6: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = G_IMPLICIT_DEF		%0:_(<6 x s16>) = G_IMPLICIT_DEF
%1:_(<6 x s16>) = G_SEXT_INREG %0, 1		%1:_(<6 x s16>) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1		S_ENDPGM 0, implicit %1

...		...

# FIXME: Should scalarize first		# FIXME: Should scalarize first
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir

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	name: test_trunc_v3s32_to_v3s16			name: test_trunc_v3s32_to_v3s16
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1_vgpr2			liveins: $vgpr0_vgpr1_vgpr2

	; CHECK-LABEL: name: test_trunc_v3s32_to_v3s16			; CHECK-LABEL: name: test_trunc_v3s32_to_v3s16
	; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
	; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF			; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)			; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
	; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[DEF]](s32)			; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
	; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)			; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR1]](<2 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
	; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<2 x s16>), [[TRUNC1]](<2 x s16>), [[DEF1]](<2 x s16>)
	; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
	; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
	; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
	; CHECK: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
	; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
	; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
	; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
	; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
	; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
	; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
	; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
	; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
	; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16)
	%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2			%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
	%1:_(<3 x s16>) = G_TRUNC %0			%1:_(<3 x s16>) = G_TRUNC %0
	%2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1			%2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1
	S_ENDPGM 0, implicit %2, implicit %3, implicit %4			S_ENDPGM 0, implicit %2, implicit %3, implicit %4
	...			...

	---			---
	name: test_trunc_v4s32_to_v4s16			name: test_trunc_v4s32_to_v4s16
	▲ Show 20 Lines • Show All 317 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir

This file was deleted.

	# RUN: not --crash llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 \| FileCheck %s

	# CHECK: LLVM ERROR: unable to legalize instruction: %1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0:_(<2 x s1>) (in function: test_unmerge_v2s1)

	---
	name: test_unmerge_v2s1
	body: \|
	bb.0:
	%0:_(<2 x s1>) = G_IMPLICIT_DEF
	%1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0
	S_NOP 0, implicit %1
	S_NOP 0, implicit %2
	...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

Show First 20 Lines • Show All 932 Lines • ▼ Show 20 Lines	bb.0:
; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>)		; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)		; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)
; CHECK: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)		; CHECK: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)
%0:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31		%0:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
%1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0		%1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1		$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2		$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
...		...

		---
		name: test_unmerge_v2s1
		body: \|
		bb.0:
		; CHECK-LABEL: name: test_unmerge_v2s1
		; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s32)
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s32)
		; CHECK: S_NOP 0, implicit [[TRUNC]](s1)
		; CHECK: S_NOP 0, implicit [[TRUNC1]](s1)
		%0:_(<2 x s1>) = G_IMPLICIT_DEF
		%1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0
		S_NOP 0, implicit %1
		S_NOP 0, implicit %2
		...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

	Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines

	---			---
	name: test_xor_v4s8			name: test_xor_v4s8
	body: \|			body: \|
	bb.0:			bb.0:

	; CHECK-LABEL: name: test_xor_v4s8			; CHECK-LABEL: name: test_xor_v4s8
	; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
	; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
	; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
	; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)			; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
	; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>)			; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
	; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)			; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
	; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)			; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
	; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[ANYEXT1]]			; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
	; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)			; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
	; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)			; CHECK: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
	; CHECK: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT2]], [[ANYEXT3]]			; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
	; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)			; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
	; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)			; CHECK: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]]
	; CHECK: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT4]], [[ANYEXT5]]			; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
	; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)			; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
	; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)			; CHECK: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY6]], [[COPY7]]
	; CHECK: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT6]], [[ANYEXT7]]			; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)			; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[XOR1]](s32)
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[XOR1]](s32)			; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[XOR2]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[XOR2]](s32)			; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[XOR3]](s32)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[XOR3]](s32)			; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
	; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
	; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
	; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)			; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
	%0:_(<4 x s8>) = G_IMPLICIT_DEF			%0:_(<4 x s8>) = G_IMPLICIT_DEF
	%1:_(<4 x s8>) = G_IMPLICIT_DEF			%1:_(<4 x s8>) = G_IMPLICIT_DEF
	%2:_(<4 x s8>) = G_XOR %0, %1			%2:_(<4 x s8>) = G_XOR %0, %1
	%3:_(<4 x s32>) = G_ANYEXT %2			%3:_(<4 x s32>) = G_ANYEXT %2
	$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3			$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
	...			...

This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNCClosedPublic

Details

Diff Detail

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Revision Contents

Diff 257380

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC
ClosedPublic