[ARM] Make remaining MVE instruction predictable

[dmgreen]

Summary

The unpredictable/hasSideEffects flag is usually inferred by tablegen from whether the instruction has a tablegen pattern (and that pattern only has a single output instruction). Now that the MVE intrinsics are all committed and producing code, the remaining instructions still marked as unpredictable need to be specially handled. This adds the flag directly to instructions that need it, notably the V*MLAL instructions and some of the MOV's.

[simon_tatham]

Do you understand why all those test outputs have changed as a side effect of this?

llvm/unittests/Target/ARM/MachineInstrTest.cpp

939–946

Typo: "unpredicatable" and "unpredictable" are not the same word, and in MVE, it is actually confusing to use the wrong one of them!

The same typo is in the headline of the commit message.

975

Another instance of the same typo.

[samparker]

Are we talking about CONSTRAINED_UNPREDICTABLE here? If so, why is this modeled with hasSideEffects?

[simon_tatham]

In D76910#1945744, @samparker wrote:

Are we talking about CONSTRAINED_UNPREDICTABLE here?

No, we're talking about MCInstrDesc::hasUnmodeledSideEffects(): not unpredictable in the sense that the architecture doesn't say what the instruction does, but just in the sense that the compiler doesn't know.

[dmgreen]

In D76910#1945744, @samparker wrote:

Are we talking about CONSTRAINED_UNPREDICTABLE here? If so, why is this modeled with hasSideEffects?

No, different thing. It is if the instruction might do things we don't model directly. Read memory, operate on unmodelled flags, those kind of things. They essentially create scheduling barriers, which is why it's good to remove them.

In D76910#1945681, @simon_tatham wrote:

Do you understand why all those test outputs have changed as a side effect of this?

The VMOV lane change I believe. They come from COPY's, not from being directly lowered. Essentially different scheduling graph -> different ordering. I don't think the tests in question are particularly interesting, just showing expansion of VLDn's that we don't have direct support for. With the schedules we have downstream this seems to help in a few cases (so long as D76909 is fixed).

llvm/unittests/Target/ARM/MachineInstrTest.cpp

975

Ah thanks. I've been doing that a lot lately.

[dmgreen]

Unpredicatable -> Unpredictable

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_ScalarShiftDoubleReg<string iname, dag iops, string asm,
                                string cstr, list<dag> pattern=[]>
   : MVE_ScalarShift<iname, (outs tGPREven:$RdaLo, tGPROdd:$RdaHi),
                     iops, asm, cstr, pattern> {
   bits<4> RdaLo;
   bits<4> RdaHi;
 
   let Inst{19-17} = RdaLo{3-1};
   let Inst{11-9} = RdaHi{3-1};
+
+  let hasSideEffects = 0;
 }
 
 class MVE_ScalarShiftDRegImm<string iname, bits<2> op5_4, bit op16,
                              list<dag> pattern=[]>
   : MVE_ScalarShiftDoubleReg<
       iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, long_shift:$imm),
       "$RdaLo, $RdaHi, $imm", "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
       pattern> {
class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
   let horizontalReduction = 1;
 
   let Predicates = [HasMVEFloat];
+  let hasSideEffects = 0;
 }
 
 multiclass MVE_VMINMAXNMV_p<string iname, bit notAbs, bit isMin,
                             MVEVectorVTInfo VTI, string intrBaseName,
                             ValueType Scalar, RegisterClass ScalarReg> {
   def "": MVE_VMINMAXNMV<iname, VTI.Suffix, VTI.Size{0}, notAbs, isMin>;
   defvar Inst        = !cast<Instruction>(NAME);
   defvar unpred_intr = !cast<Intrinsic>(intrBaseName);
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
   let Inst{15-13} = RdaLoDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
   let horizontalReduction = 1;
+
+  let hasSideEffects = 0;
 }
 
 multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
                                bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
                                list<dag> pattern=[]> {
   def ""#x#suffix : MVE_VMLALDAVBase<
      iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
      sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
class MVE_VMOV_lane<string suffix, bit U, dag indexop,
   let Inst{31-24} = 0b11101110;
   let Inst{23} = U;
   let Inst{20} = dir.bit_20;
   let Inst{19-17} = Qd{2-0};
   let Inst{15-12} = Rt{3-0};
   let Inst{11-8} = 0b1011;
   let Inst{7} = Qd{3};
   let Inst{4-0} = 0b10000;
+
+  let hasSideEffects = 0;
 }
 
 class MVE_VMOV_lane_32<MVE_VMOV_lane_direction dir>
     : MVE_VMOV_lane<"32", 0b0, (ins MVEVectorIndex<4>:$Idx), dir> {
   bits<2> Idx;
   let Inst{22} = 0b0;
   let Inst{6-5} = 0b00;
   let Inst{16} = Idx{1};
class MVE_VFMAMLA_qr<string iname, string suffix,
 
   let Inst{28} = bit_28;
   let Inst{21-20} = bits_21_20;
   let Inst{16} = 0b1;
   let Inst{12} = S;
   let Inst{8} = 0b0;
   let Inst{5} = 0b0;
   let validForTailPredication = 1;
+  let hasSideEffects = 0;
 }
 
 multiclass MVE_VMLA_qr_multi<string iname, MVEVectorVTInfo VTI,
                              bit scalar_addend> {
   def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
                          scalar_addend>;
   defvar Inst = !cast<Instruction>(NAME);
   defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_n_predicated");
class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
   let Inst{16} = 0b1;
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = bit_12;
   let Inst{11-8} = 0b1111;
   let Inst{7} = imm{1};
   let Inst{6-1} = 0b110111;
   let Inst{0} = imm{0};
   let validForTailPredication = 1;
+  let hasSideEffects = 0;
 }
 
 def MVE_VIDUPu8  : MVE_VxDUP<"vidup", "u8",  0b00, 0b0>;
 def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0>;
 def MVE_VIDUPu32 : MVE_VxDUP<"vidup", "u32", 0b10, 0b0>;
 
 def MVE_VDDUPu8  : MVE_VxDUP<"vddup", "u8",  0b00, 0b1>;
 def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1>;
class MVE_VxWDUP<string iname, string suffix, bits<2> size, bit bit_12,
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = bit_12;
   let Inst{11-8} = 0b1111;
   let Inst{7} = imm{1};
   let Inst{6-4} = 0b110;
   let Inst{3-1} = Rm{3-1};
   let Inst{0} = imm{0};
   let validForTailPredication = 1;
+  let hasSideEffects = 0;
 }
 
 def MVE_VIWDUPu8  : MVE_VxWDUP<"viwdup", "u8",  0b00, 0b0>;
 def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
 def MVE_VIWDUPu32 : MVE_VxWDUP<"viwdup", "u32", 0b10, 0b0>;
 
 def MVE_VDWDUPu8  : MVE_VxWDUP<"vdwdup", "u8",  0b00, 0b1>;
 def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
class MVE_VMOV_64bit<dag oops, dag iops, bit to_qreg, string ops, string cstr>
   let Inst{22} = Qd{3};
   let Inst{21} = 0b0;
   let Inst{20} = to_qreg;
   let Inst{19-16} = Rt2{3-0};
   let Inst{15-13} = Qd{2-0};
   let Inst{12-5} = 0b01111000;
   let Inst{4} = idx2;
   let Inst{3-0} = Rt{3-0};
+
+  let hasSideEffects = 0;
 }
 
 // The assembly syntax for these instructions mentions the vector
 // register name twice, e.g.
 //
 //    vmov q2[2], q2[0], r0, r1
 //    vmov r0, r1, q2[2], q2[0]
 //

llvm/test/CodeGen/Thumb2/mve-vld3.ll

 }
 
 define void @vld3_v8i32(<24 x i32> *%src, <8 x i32> *%dst) {
 ; CHECK-LABEL: vld3_v8i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #80]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.f32 s12, s5
-; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vmov.32 r2, q2[2]
+; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vdup.32 q4, r2
 ; CHECK-NEXT:    vmov.f32 s14, s3
-; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vmov.32 r2, q2[1]
-; CHECK-NEXT:    vmov.f64 d8, d2
+; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vdup.32 q5, r2
+; CHECK-NEXT:    vmov.f64 d8, d2
 ; CHECK-NEXT:    vmov.f32 s17, s7
 ; CHECK-NEXT:    vmov.f32 s18, s2
 ; CHECK-NEXT:    vmov.f32 s0, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.f32 s10, s8
 ; CHECK-NEXT:    vadd.i32 q3, q4, q3
 ; CHECK-NEXT:    vmov.f32 s2, s8
 ; CHECK-NEXT:    vmov.f32 s3, s11
 ; CHECK-NEXT:    vldrw.u32 q2, [r0]
 ; CHECK-NEXT:    vadd.i32 q0, q3, q0
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s16, s9
+; CHECK-NEXT:    vstrw.32 q0, [r1, #16]
 ; CHECK-NEXT:    vmov.f32 s17, s4
 ; CHECK-NEXT:    vmov.32 r0, q3[2]
 ; CHECK-NEXT:    vdup.32 q5, r0
 ; CHECK-NEXT:    vmov.f32 s18, s7
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.32 r0, q3[1]
 ; CHECK-NEXT:    vmov.f64 d10, d4
 ; CHECK-NEXT:    vdup.32 q6, r0
-; CHECK-NEXT:    vstrw.32 q0, [r1, #16]
 ; CHECK-NEXT:    vmov.f32 s21, s11
 ; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vmov.f32 s4, s10
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.f32 s14, s12
 ; CHECK-NEXT:    vadd.i32 q4, q5, q4
 ; CHECK-NEXT:    vmov.f32 s6, s12
 ; CHECK-NEXT:    vmov.f32 s7, s15

 define void @vld3_v16i32(<48 x i32> *%src, <16 x i32> *%dst) {
 ; CHECK-LABEL: vld3_v16i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #80]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.f32 s12, s5
-; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vmov.32 r2, q2[2]
+; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vdup.32 q4, r2
 ; CHECK-NEXT:    vmov.f32 s14, s3
-; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vmov.32 r2, q2[1]
-; CHECK-NEXT:    vmov.f64 d8, d2
+; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vdup.32 q5, r2
+; CHECK-NEXT:    vmov.f64 d8, d2
 ; CHECK-NEXT:    vmov.f32 s17, s7
 ; CHECK-NEXT:    vmov.f32 s18, s2
 ; CHECK-NEXT:    vmov.f32 s0, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.f32 s10, s8
 ; CHECK-NEXT:    vadd.i32 q3, q4, q3
 ; CHECK-NEXT:    vmov.f32 s2, s8
 ; CHECK-NEXT:    vmov.f32 s3, s11
 ; CHECK-NEXT:    vldrw.u32 q2, [r0]
 ; CHECK-NEXT:    vadd.i32 q0, q3, q0
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s16, s9
 ; CHECK-NEXT:    vstrw.32 q0, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s17, s4
 ; CHECK-NEXT:    vmov.32 r2, q3[2]
 ; CHECK-NEXT:    vdup.32 q5, r2
 ; CHECK-NEXT:    vmov.f32 s18, s7
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.32 r2, q3[1]
 ; CHECK-NEXT:    vmov.f64 d10, d4
 ; CHECK-NEXT:    vdup.32 q6, r2
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #128]
 ; CHECK-NEXT:    vmov.f32 s21, s11
 ; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vmov.f32 s4, s10
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #160]
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.f32 s14, s12
 ; CHECK-NEXT:    vadd.i32 q4, q5, q4
 ; CHECK-NEXT:    vmov.f32 s6, s12
 ; CHECK-NEXT:    vmov.f32 s7, s15
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #144]
 ; CHECK-NEXT:    vadd.i32 q1, q4, q1
 ; CHECK-NEXT:    vldrw.u32 q4, [r0, #176]
 ; CHECK-NEXT:    vmov.f32 s20, s13
 ; CHECK-NEXT:    vmov.f32 s21, s8
 ; CHECK-NEXT:    vmov.32 r2, q4[2]
 ; CHECK-NEXT:    vdup.32 q6, r2
 ; CHECK-NEXT:    vmov.f32 s22, s11
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.32 r2, q4[1]
 ; CHECK-NEXT:    vmov.f64 d12, d6
 ; CHECK-NEXT:    vdup.32 q7, r2
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #128]
 ; CHECK-NEXT:    vmov.f32 s25, s15
 ; CHECK-NEXT:    vmov.f32 s26, s10
 ; CHECK-NEXT:    vmov.f32 s8, s14
 ; CHECK-NEXT:    vmov.f32 s27, s31
 ; CHECK-NEXT:    vmov.f32 s18, s16
 ; CHECK-NEXT:    vadd.i32 q5, q6, q5
 ; CHECK-NEXT:    vmov.f32 s10, s16
 ; CHECK-NEXT:    vmov.f32 s11, s19

 }
 
 define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) {
 ; CHECK-LABEL: vld3_v8f32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #80]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.f32 s12, s5
-; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vmov.32 r2, q2[2]
+; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vdup.32 q4, r2
 ; CHECK-NEXT:    vmov.f32 s14, s3
-; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vmov.32 r2, q2[1]
-; CHECK-NEXT:    vmov.f64 d8, d2
+; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vdup.32 q5, r2
+; CHECK-NEXT:    vmov.f64 d8, d2
 ; CHECK-NEXT:    vmov.f32 s17, s7
 ; CHECK-NEXT:    vmov.f32 s18, s2
 ; CHECK-NEXT:    vmov.f32 s0, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.f32 s10, s8
 ; CHECK-NEXT:    vadd.f32 q3, q4, q3
 ; CHECK-NEXT:    vmov.f32 s2, s8
 ; CHECK-NEXT:    vmov.f32 s3, s11
 ; CHECK-NEXT:    vldrw.u32 q2, [r0]
 ; CHECK-NEXT:    vadd.f32 q0, q3, q0
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s16, s9
+; CHECK-NEXT:    vstrw.32 q0, [r1, #16]
 ; CHECK-NEXT:    vmov.f32 s17, s4
 ; CHECK-NEXT:    vmov.32 r0, q3[2]
 ; CHECK-NEXT:    vdup.32 q5, r0
 ; CHECK-NEXT:    vmov.f32 s18, s7
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.32 r0, q3[1]
 ; CHECK-NEXT:    vmov.f64 d10, d4
 ; CHECK-NEXT:    vdup.32 q6, r0
-; CHECK-NEXT:    vstrw.32 q0, [r1, #16]
 ; CHECK-NEXT:    vmov.f32 s21, s11
 ; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vmov.f32 s4, s10
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.f32 s14, s12
 ; CHECK-NEXT:    vadd.f32 q4, q5, q4
 ; CHECK-NEXT:    vmov.f32 s6, s12
 ; CHECK-NEXT:    vmov.f32 s7, s15

 define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) {
 ; CHECK-LABEL: vld3_v16f32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #80]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.f32 s12, s5
-; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vmov.32 r2, q2[2]
+; CHECK-NEXT:    vmov.f32 s13, s0
 ; CHECK-NEXT:    vdup.32 q4, r2
 ; CHECK-NEXT:    vmov.f32 s14, s3
-; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vmov.32 r2, q2[1]
-; CHECK-NEXT:    vmov.f64 d8, d2
+; CHECK-NEXT:    vmov.f32 s15, s19
 ; CHECK-NEXT:    vdup.32 q5, r2
+; CHECK-NEXT:    vmov.f64 d8, d2
 ; CHECK-NEXT:    vmov.f32 s17, s7
 ; CHECK-NEXT:    vmov.f32 s18, s2
 ; CHECK-NEXT:    vmov.f32 s0, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.f32 s10, s8
 ; CHECK-NEXT:    vadd.f32 q3, q4, q3
 ; CHECK-NEXT:    vmov.f32 s2, s8
 ; CHECK-NEXT:    vmov.f32 s3, s11
 ; CHECK-NEXT:    vldrw.u32 q2, [r0]
 ; CHECK-NEXT:    vadd.f32 q0, q3, q0
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s16, s9
 ; CHECK-NEXT:    vstrw.32 q0, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s17, s4
 ; CHECK-NEXT:    vmov.32 r2, q3[2]
 ; CHECK-NEXT:    vdup.32 q5, r2
 ; CHECK-NEXT:    vmov.f32 s18, s7
 ; CHECK-NEXT:    vmov.f32 s19, s23
 ; CHECK-NEXT:    vmov.32 r2, q3[1]
 ; CHECK-NEXT:    vmov.f64 d10, d4
 ; CHECK-NEXT:    vdup.32 q6, r2
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #128]
 ; CHECK-NEXT:    vmov.f32 s21, s11
 ; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vmov.f32 s4, s10
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #160]
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.f32 s14, s12
 ; CHECK-NEXT:    vadd.f32 q4, q5, q4
 ; CHECK-NEXT:    vmov.f32 s6, s12
 ; CHECK-NEXT:    vmov.f32 s7, s15
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #144]
 ; CHECK-NEXT:    vadd.f32 q1, q4, q1
 ; CHECK-NEXT:    vldrw.u32 q4, [r0, #176]
 ; CHECK-NEXT:    vmov.f32 s20, s13
 ; CHECK-NEXT:    vmov.f32 s21, s8
 ; CHECK-NEXT:    vmov.32 r2, q4[2]
 ; CHECK-NEXT:    vdup.32 q6, r2
 ; CHECK-NEXT:    vmov.f32 s22, s11
 ; CHECK-NEXT:    vmov.f32 s23, s27
 ; CHECK-NEXT:    vmov.32 r2, q4[1]
 ; CHECK-NEXT:    vmov.f64 d12, d6
 ; CHECK-NEXT:    vdup.32 q7, r2
-; CHECK-NEXT:    vldrw.u32 q0, [r0, #128]
 ; CHECK-NEXT:    vmov.f32 s25, s15
 ; CHECK-NEXT:    vmov.f32 s26, s10
 ; CHECK-NEXT:    vmov.f32 s8, s14
 ; CHECK-NEXT:    vmov.f32 s27, s31
 ; CHECK-NEXT:    vmov.f32 s18, s16
 ; CHECK-NEXT:    vadd.f32 q5, q6, q5
 ; CHECK-NEXT:    vmov.f32 s10, s16
 ; CHECK-NEXT:    vmov.f32 s11, s19

llvm/test/CodeGen/Thumb2/mve-vld4.ll

 ; CHECK-NEXT:    vdup.32 q1, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    vmov r0, s10
 ; CHECK-NEXT:    add r0, r2
 ; CHECK-NEXT:    vmov r2, s14
 ; CHECK-NEXT:    add r2, r3
 ; CHECK-NEXT:    vmov r3, s0
 ; CHECK-NEXT:    add r0, r2
-; CHECK-NEXT:    str r0, [r1, #4]
 ; CHECK-NEXT:    vmov.32 r2, q0[2]
-; CHECK-NEXT:    vmov r0, s8
 ; CHECK-NEXT:    vdup.32 q1, r2
+; CHECK-NEXT:    str r0, [r1, #4]
+; CHECK-NEXT:    vmov r0, s8
 ; CHECK-NEXT:    vmov r2, s4
 ; CHECK-NEXT:    add r0, r2
 ; CHECK-NEXT:    vmov r2, s12
 ; CHECK-NEXT:    add r2, r3
 ; CHECK-NEXT:    add r0, r2
 ; CHECK-NEXT:    str r0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:

llvm/test/CodeGen/Thumb2/mve-vst3.ll

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    .pad #48
 ; CHECK-NEXT:    sub sp, #48
 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #80]
 ; CHECK-NEXT:    vldrw.u32 q5, [r0, #16]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vmov.f64 d6, d1
-; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vldrw.u32 q4, [r0]
+; CHECK-NEXT:    vmov.f64 d6, d1
 ; CHECK-NEXT:    vldrw.u32 q6, [r0, #32]
-; CHECK-NEXT:    vdup.32 q2, r2
+; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vldrw.u32 q7, [r0, #64]
+; CHECK-NEXT:    vdup.32 q2, r2
 ; CHECK-NEXT:    vstrw.32 q4, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT:    vstrw.32 q5, [sp] @ 16-byte Spill
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f32 s13, s23
 ; CHECK-NEXT:    vstrw.32 q6, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s15, s3
-; CHECK-NEXT:    vstrw.32 q5, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s14, s10
-; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f64 d4, d8
+; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s9, s24
 ; CHECK-NEXT:    vmov.f32 s11, s17
 ; CHECK-NEXT:    vmov q4, q5
 ; CHECK-NEXT:    vmov.f32 s21, s4
 ; CHECK-NEXT:    vmov.f32 s23, s17
 ; CHECK-NEXT:    vdup.32 q4, r0
 ; CHECK-NEXT:    vmov.32 r0, q0[0]
 ; CHECK-NEXT:    vmov.f32 s0, s5
 ; CHECK-NEXT:    vmov.f32 s10, s18
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s3, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vdup.32 q6, r0
+; CHECK-NEXT:    vmov.32 r0, q4[3]
 ; CHECK-NEXT:    vmov.f32 s22, s26
 ; CHECK-NEXT:    vldrw.u32 q6, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s2, s6
-; CHECK-NEXT:    vmov.32 r0, q4[3]
-; CHECK-NEXT:    vmov.f32 s4, s17
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #48]
-; CHECK-NEXT:    vmov.f32 s5, s29
+; CHECK-NEXT:    vmov.f32 s4, s17
 ; CHECK-NEXT:    vstrw.32 q0, [r1, #64]
+; CHECK-NEXT:    vmov.f32 s5, s29
+; CHECK-NEXT:    vstrw.32 q2, [r1]
 ; CHECK-NEXT:    vmov.f32 s28, s30
-; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s7, s18
 ; CHECK-NEXT:    vdup.32 q4, r0
 ; CHECK-NEXT:    vmov.f32 s29, s27
-; CHECK-NEXT:    vstrw.32 q2, [r1]
 ; CHECK-NEXT:    vmov.f32 s6, s26
 ; CHECK-NEXT:    vmov.f32 s30, s18
 ; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vstrw.32 q7, [r1, #32]
 ; CHECK-NEXT:    add sp, #48
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    bx lr
 entry:

 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #48]
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s6, s22
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #112]
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f64 d4, d15
 ; CHECK-NEXT:    vldrw.u32 q4, [r0, #176]
-; CHECK-NEXT:    vstrw.32 q0, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vmov.32 r0, q6[3]
+; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vdup.32 q1, r0
+; CHECK-NEXT:    vmov.32 r0, q3[3]
+; CHECK-NEXT:    vstrw.32 q0, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s9, s23
 ; CHECK-NEXT:    vmov.f32 s11, s31
 ; CHECK-NEXT:    vmov.f32 s10, s6
 ; CHECK-NEXT:    vmov.f64 d2, d9
 ; CHECK-NEXT:    vstrw.32 q2, [r1, #32]
-; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov.f32 s5, s3
 ; CHECK-NEXT:    vmov.f32 s7, s19
 ; CHECK-NEXT:    vmov q2, q1
 ; CHECK-NEXT:    vdup.32 q1, r0
 ; CHECK-NEXT:    vmov.f32 s10, s6
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f64 d2, d10
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vldrw.u32 q2, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vdup.32 q0, r0
+; CHECK-NEXT:    vmov.32 r0, q4[0]
 ; CHECK-NEXT:    vmov.f32 s5, s24
 ; CHECK-NEXT:    vmov.f32 s7, s21
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vmov.f64 d0, d4
 ; CHECK-NEXT:    vstrw.32 q1, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q4[0]
 ; CHECK-NEXT:    vmov.f32 s1, s12
 ; CHECK-NEXT:    vmov.f32 s3, s9
 ; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #112] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q1, [sp, #48] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #96] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s16, s13
 ; CHECK-NEXT:    vmov.f32 s24, s5
 ; CHECK-NEXT:    vmov.f32 s25, s1
 ; CHECK-NEXT:    vmov.f32 s19, s14
 ; CHECK-NEXT:    vmov q3, q1
 ; CHECK-NEXT:    vmov.f32 s27, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s18, s10
+; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov.f64 d4, d1
 ; CHECK-NEXT:    vstrw.32 q4, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov q5, q1
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s9, s7
 ; CHECK-NEXT:    vmov.f32 s11, s3
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s10, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s26, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #128] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f64 d6, d1
 ; CHECK-NEXT:    vmov.32 r0, q4[3]
 ; CHECK-NEXT:    vmov q7, q0
+; CHECK-NEXT:    vstrw.32 q6, [r1, #112]
+; CHECK-NEXT:    vstrw.32 q2, [r1, #128]
 ; CHECK-NEXT:    vmov.f32 s13, s7
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #96] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s15, s3
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s14, s2
 ; CHECK-NEXT:    vmov q0, q5
 ; CHECK-NEXT:    vmov.f32 s21, s4
+; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s23, s1
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #112] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.32 r0, q0[0]
 ; CHECK-NEXT:    vdup.32 q0, r0
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f32 s22, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT:    vmov.32 r0, q7[0]
-; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
-; CHECK-NEXT:    vmov.f64 d2, d0
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #96]
-; CHECK-NEXT:    vstrw.32 q6, [r1, #112]
-; CHECK-NEXT:    vstrw.32 q2, [r1, #128]
+; CHECK-NEXT:    vmov.f64 d2, d0
 ; CHECK-NEXT:    vmov.f32 s5, s16
 ; CHECK-NEXT:    vmov q4, q0
 ; CHECK-NEXT:    vmov.f32 s7, s1
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q1, [r1, #48]
 ; CHECK-NEXT:    vmov.f32 s28, s1

 ; CHECK-NEXT:    vmov.16 q2[4], r2
 ; CHECK-NEXT:    vmov.u16 r2, q0[2]
 ; CHECK-NEXT:    vmov.16 q2[6], r2
 ; CHECK-NEXT:    vmov.u16 r2, q1[2]
 ; CHECK-NEXT:    vmov.16 q2[7], r2
 ; CHECK-NEXT:    vmov q7, q1
 ; CHECK-NEXT:    vmov.f32 s9, s0
 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #80]
-; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.u16 r2, q2[3]
+; CHECK-NEXT:    vmov q3, q2
 ; CHECK-NEXT:    vmov.32 r3, q0[0]
 ; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    vdup.32 q0, r3
-; CHECK-NEXT:    vmov q3, q2
+; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.u16 r3, q0[2]
+; CHECK-NEXT:    vstrw.32 q7, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q2[2], r3
 ; CHECK-NEXT:    vmov.16 q2[3], r2
 ; CHECK-NEXT:    vmov.u16 r2, q3[4]
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #32]
 ; CHECK-NEXT:    vmov.16 q2[4], r2
 ; CHECK-NEXT:    vmov.u16 r2, q0[5]
 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.16 q2[5], r2

 ; CHECK-NEXT:    vmov.u16 r0, q1[5]
 ; CHECK-NEXT:    vmov.16 q0[1], r0
 ; CHECK-NEXT:    vmov.u16 r0, q7[6]
 ; CHECK-NEXT:    vmov.16 q0[3], r0
 ; CHECK-NEXT:    vmov.u16 r0, q7[7]
 ; CHECK-NEXT:    vmov.16 q0[6], r0
 ; CHECK-NEXT:    vmov.u16 r0, q1[7]
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT:    vstrw.32 q2, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT:    vstrw.32 q7, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q0[7], r0
-; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vmov.f32 s2, s19
-; CHECK-NEXT:    vdup.32 q7, r2
+; CHECK-NEXT:    vstrw.32 q2, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-NEXT:    vmov.u16 r2, q7[2]
+; CHECK-NEXT:    vdup.32 q7, r2
 ; CHECK-NEXT:    vrev32.16 q3, q3
-; CHECK-NEXT:    vmov.16 q2[2], r2
+; CHECK-NEXT:    vmov.u16 r2, q7[2]
 ; CHECK-NEXT:    vstrw.32 q3, [sp] @ 16-byte Spill
+; CHECK-NEXT:    vmov.16 q2[2], r2
+; CHECK-NEXT:    vstrw.32 q4, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q2[3], r0
 ; CHECK-NEXT:    vmov.u16 r0, q0[4]
 ; CHECK-NEXT:    vmov.16 q2[4], r0
 ; CHECK-NEXT:    vmov.u16 r0, q7[5]
 ; CHECK-NEXT:    vmov.16 q2[5], r0
 ; CHECK-NEXT:    vmov.u16 r0, q4[2]
 ; CHECK-NEXT:    vmov.16 q3[0], r0
 ; CHECK-NEXT:    vmov.u16 r0, q1[3]
 ; CHECK-NEXT:    vmov.16 q3[1], r0
 ; CHECK-NEXT:    vmov.u16 r0, q4[4]
 ; CHECK-NEXT:    vldrw.u32 q7, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.16 q3[6], r0
 ; CHECK-NEXT:    vmov.u16 r0, q1[5]
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #144] @ 16-byte Reload
-; CHECK-NEXT:    vstrw.32 q4, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vrev32.16 q7, q7
 ; CHECK-NEXT:    vmov.16 q3[7], r0
 ; CHECK-NEXT:    vmov.u16 r0, q1[2]
 ; CHECK-NEXT:    vstrw.32 q7, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q7[0], r0
 ; CHECK-NEXT:    vmov.u16 r0, q4[3]
+; CHECK-NEXT:    vmov.f32 s1, s9
 ; CHECK-NEXT:    vmov.16 q7[1], r0
 ; CHECK-NEXT:    vmov.u16 r0, q1[4]
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #64] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s1, s9
 ; CHECK-NEXT:    vmov.f32 s2, s10
 ; CHECK-NEXT:    vldrw.u32 q2, [sp, #96] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s25, s5
 ; CHECK-NEXT:    vmov.16 q7[6], r0
+; CHECK-NEXT:    vmov.f32 s25, s5
+; CHECK-NEXT:    vmov.u16 r0, q4[5]
 ; CHECK-NEXT:    vmov.f32 s26, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #80] @ 16-byte Reload
-; CHECK-NEXT:    vmov.u16 r0, q4[5]
 ; CHECK-NEXT:    vstrw.32 q0, [r1, #80]
-; CHECK-NEXT:    vmov.f32 s21, s5
 ; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s21, s5
+; CHECK-NEXT:    vmov.16 q7[7], r0
 ; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #112] @ 16-byte Reload
-; CHECK-NEXT:    vmov.16 q7[7], r0
 ; CHECK-NEXT:    vmov.u16 r2, q0[2]
-; CHECK-NEXT:    vmov.f32 s9, s5
 ; CHECK-NEXT:    vmov.u16 r0, q0[5]
+; CHECK-NEXT:    vmov.f32 s9, s5
+; CHECK-NEXT:    vmov.16 q0[2], r2
 ; CHECK-NEXT:    vmov.f32 s10, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #144] @ 16-byte Reload
-; CHECK-NEXT:    vmov.16 q0[2], r2
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #32]
+; CHECK-NEXT:    vstrw.32 q2, [r1, #48]
 ; CHECK-NEXT:    vmov.f32 s29, s5
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s30, s18
-; CHECK-NEXT:    vstrw.32 q2, [r1, #48]
+; CHECK-NEXT:    vstrw.32 q6, [r1]
 ; CHECK-NEXT:    vmov.u16 r2, q7[3]
 ; CHECK-NEXT:    vmov.f32 s13, s5
 ; CHECK-NEXT:    vmov.16 q0[3], r2
 ; CHECK-NEXT:    vmov.u16 r2, q7[4]
 ; CHECK-NEXT:    vmov.16 q0[4], r2
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #128] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.16 q0[5], r0
-; CHECK-NEXT:    vstrw.32 q6, [r1]
 ; CHECK-NEXT:    vmov.f32 s29, s1
 ; CHECK-NEXT:    vmov.f32 s30, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s14, s6
 ; CHECK-NEXT:    vstrw.32 q7, [r1, #16]
 ; CHECK-NEXT:    vmov.u16 r2, q0[2]
 ; CHECK-NEXT:    vmov.u16 r0, q0[5]
 ; CHECK-NEXT:    vmov.16 q0[2], r2

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    .pad #48
 ; CHECK-NEXT:    sub sp, #48
 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #80]
 ; CHECK-NEXT:    vldrw.u32 q5, [r0, #16]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT:    vmov.f64 d6, d1
-; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vldrw.u32 q4, [r0]
+; CHECK-NEXT:    vmov.f64 d6, d1
 ; CHECK-NEXT:    vldrw.u32 q6, [r0, #32]
-; CHECK-NEXT:    vdup.32 q2, r2
+; CHECK-NEXT:    vmov.32 r2, q1[3]
 ; CHECK-NEXT:    vldrw.u32 q7, [r0, #64]
+; CHECK-NEXT:    vdup.32 q2, r2
 ; CHECK-NEXT:    vstrw.32 q4, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT:    vstrw.32 q5, [sp] @ 16-byte Spill
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f32 s13, s23
 ; CHECK-NEXT:    vstrw.32 q6, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s15, s3
-; CHECK-NEXT:    vstrw.32 q5, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s14, s10
-; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f64 d4, d8
+; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s9, s24
 ; CHECK-NEXT:    vmov.f32 s11, s17
 ; CHECK-NEXT:    vmov q4, q5
 ; CHECK-NEXT:    vmov.f32 s21, s4
 ; CHECK-NEXT:    vmov.f32 s23, s17
 ; CHECK-NEXT:    vdup.32 q4, r0
 ; CHECK-NEXT:    vmov.32 r0, q0[0]
 ; CHECK-NEXT:    vmov.f32 s0, s5
 ; CHECK-NEXT:    vmov.f32 s10, s18
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s3, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vdup.32 q6, r0
+; CHECK-NEXT:    vmov.32 r0, q4[3]
 ; CHECK-NEXT:    vmov.f32 s22, s26
 ; CHECK-NEXT:    vldrw.u32 q6, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s2, s6
-; CHECK-NEXT:    vmov.32 r0, q4[3]
-; CHECK-NEXT:    vmov.f32 s4, s17
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #48]
-; CHECK-NEXT:    vmov.f32 s5, s29
+; CHECK-NEXT:    vmov.f32 s4, s17
 ; CHECK-NEXT:    vstrw.32 q0, [r1, #64]
+; CHECK-NEXT:    vmov.f32 s5, s29
+; CHECK-NEXT:    vstrw.32 q2, [r1]
 ; CHECK-NEXT:    vmov.f32 s28, s30
-; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s7, s18
 ; CHECK-NEXT:    vdup.32 q4, r0
 ; CHECK-NEXT:    vmov.f32 s29, s27
-; CHECK-NEXT:    vstrw.32 q2, [r1]
 ; CHECK-NEXT:    vmov.f32 s6, s26
 ; CHECK-NEXT:    vmov.f32 s30, s18
 ; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vstrw.32 q7, [r1, #32]
 ; CHECK-NEXT:    add sp, #48
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    bx lr
 entry:

 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #48]
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #32]
 ; CHECK-NEXT:    vmov.f32 s6, s22
 ; CHECK-NEXT:    vldrw.u32 q3, [r0, #112]
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #16] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f64 d4, d15
 ; CHECK-NEXT:    vldrw.u32 q4, [r0, #176]
-; CHECK-NEXT:    vstrw.32 q0, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vmov.32 r0, q6[3]
+; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vdup.32 q1, r0
+; CHECK-NEXT:    vmov.32 r0, q3[3]
+; CHECK-NEXT:    vstrw.32 q0, [sp, #32] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s9, s23
 ; CHECK-NEXT:    vmov.f32 s11, s31
 ; CHECK-NEXT:    vmov.f32 s10, s6
 ; CHECK-NEXT:    vmov.f64 d2, d9
 ; CHECK-NEXT:    vstrw.32 q2, [r1, #32]
-; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov.f32 s5, s3
 ; CHECK-NEXT:    vmov.f32 s7, s19
 ; CHECK-NEXT:    vmov q2, q1
 ; CHECK-NEXT:    vdup.32 q1, r0
 ; CHECK-NEXT:    vmov.f32 s10, s6
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f64 d2, d10
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vldrw.u32 q2, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vdup.32 q0, r0
+; CHECK-NEXT:    vmov.32 r0, q4[0]
 ; CHECK-NEXT:    vmov.f32 s5, s24
 ; CHECK-NEXT:    vmov.f32 s7, s21
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vmov.f64 d0, d4
 ; CHECK-NEXT:    vstrw.32 q1, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q4[0]
 ; CHECK-NEXT:    vmov.f32 s1, s12
 ; CHECK-NEXT:    vmov.f32 s3, s9
 ; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #112] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q1, [sp, #48] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #96] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s16, s13
 ; CHECK-NEXT:    vmov.f32 s24, s5
 ; CHECK-NEXT:    vmov.f32 s25, s1
 ; CHECK-NEXT:    vmov.f32 s19, s14
 ; CHECK-NEXT:    vmov q3, q1
 ; CHECK-NEXT:    vmov.f32 s27, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s18, s10
+; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov.f64 d4, d1
 ; CHECK-NEXT:    vstrw.32 q4, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r0, q3[3]
 ; CHECK-NEXT:    vmov q5, q1
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s9, s7
 ; CHECK-NEXT:    vmov.f32 s11, s3
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s10, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s26, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #128] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f64 d6, d1
 ; CHECK-NEXT:    vmov.32 r0, q4[3]
 ; CHECK-NEXT:    vmov q7, q0
+; CHECK-NEXT:    vstrw.32 q6, [r1, #112]
+; CHECK-NEXT:    vstrw.32 q2, [r1, #128]
 ; CHECK-NEXT:    vmov.f32 s13, s7
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #96] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s15, s3
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s14, s2
 ; CHECK-NEXT:    vmov q0, q5
 ; CHECK-NEXT:    vmov.f32 s21, s4
+; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
 ; CHECK-NEXT:    vmov.f32 s23, s1
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #112] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.32 r0, q0[0]
 ; CHECK-NEXT:    vdup.32 q0, r0
+; CHECK-NEXT:    vmov.32 r0, q7[0]
 ; CHECK-NEXT:    vmov.f32 s22, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT:    vmov.32 r0, q7[0]
-; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
-; CHECK-NEXT:    vmov.f64 d2, d0
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #96]
-; CHECK-NEXT:    vstrw.32 q6, [r1, #112]
-; CHECK-NEXT:    vstrw.32 q2, [r1, #128]
+; CHECK-NEXT:    vmov.f64 d2, d0
 ; CHECK-NEXT:    vmov.f32 s5, s16
 ; CHECK-NEXT:    vmov q4, q0
 ; CHECK-NEXT:    vmov.f32 s7, s1
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vmov.f32 s6, s2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q1, [r1, #48]
 ; CHECK-NEXT:    vmov.f32 s28, s1

 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    vldrw.u32 q2, [r0]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
 ; CHECK-NEXT:    vldrw.u32 q5, [r0, #32]
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmovx.f16 s12, s4
 ; CHECK-NEXT:    vmov r2, s4
 ; CHECK-NEXT:    vmov.16 q0[0], r3
-; CHECK-NEXT:    vmov.32 r0, q5[0]
 ; CHECK-NEXT:    vmov.16 q0[1], r2
 ; CHECK-NEXT:    vmov r2, s12
-; CHECK-NEXT:    vdup.32 q4, r0
+; CHECK-NEXT:    vmov.32 r0, q5[0]
 ; CHECK-NEXT:    vmov.16 q0[4], r2
+; CHECK-NEXT:    vdup.32 q4, r0
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov.16 q0[6], r2
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    vmovx.f16 s12, s8
 ; CHECK-NEXT:    vmov r0, s17
 ; CHECK-NEXT:    vmov.16 q0[7], r2
 ; CHECK-NEXT:    vmov r2, s12
 ; CHECK-NEXT:    vmov.16 q3[2], r0

 ; CHECK-NEXT:    vmov.16 q4[0], r0
 ; CHECK-NEXT:    vmov.16 q4[1], r2
 ; CHECK-NEXT:    vmov r0, s7
 ; CHECK-NEXT:    vmov.16 q4[3], r0
 ; CHECK-NEXT:    vmov r0, s24
 ; CHECK-NEXT:    vmovx.f16 s24, s23
 ; CHECK-NEXT:    vmov.16 q4[6], r0
 ; CHECK-NEXT:    vmov r0, s24
-; CHECK-NEXT:    vstrw.32 q1, [sp] @ 16-byte Spill
-; CHECK-NEXT:    vmov.16 q4[7], r0
 ; CHECK-NEXT:    vmov.32 r2, q2[3]
-; CHECK-NEXT:    vmov.f32 s18, s23
+; CHECK-NEXT:    vmov.16 q4[7], r0
 ; CHECK-NEXT:    vdup.32 q7, r2
+; CHECK-NEXT:    vmov.f32 s18, s23
 ; CHECK-NEXT:    vmovx.f16 s24, s17
 ; CHECK-NEXT:    vmov r2, s29
+; CHECK-NEXT:    vmovx.f16 s28, s30
 ; CHECK-NEXT:    vmov r0, s24
 ; CHECK-NEXT:    vmov.16 q6[2], r2
 ; CHECK-NEXT:    vmov.16 q6[3], r0
-; CHECK-NEXT:    vmovx.f16 s28, s30
+; CHECK-NEXT:    vstrw.32 q1, [sp] @ 16-byte Spill
 ; CHECK-NEXT:    vmovx.f16 s4, s10
 ; CHECK-NEXT:    vmov.f32 s1, s13
 ; CHECK-NEXT:    vmov.f32 s2, s14
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    vmov r0, s18
 ; CHECK-NEXT:    vmov.16 q6[4], r0
 ; CHECK-NEXT:    vmov r0, s28
 ; CHECK-NEXT:    vmov.16 q6[5], r0

 ; CHECK-NEXT:    vmov.16 q1[4], r2
 ; CHECK-NEXT:    vmov r2, s13
 ; CHECK-NEXT:    vmov.16 q1[6], r2
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov.16 q1[7], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vldrw.u32 q0, [r0, #64]
 ; CHECK-NEXT:    vmov.f32 s5, s12
+; CHECK-NEXT:    vmov q5, q3
 ; CHECK-NEXT:    vstrw.32 q3, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vstrw.32 q1, [sp, #128] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.32 r3, q0[0]
 ; CHECK-NEXT:    vmov q4, q0
 ; CHECK-NEXT:    vdup.32 q0, r3
-; CHECK-NEXT:    vmov q5, q3
+; CHECK-NEXT:    vstrw.32 q1, [sp, #128] @ 16-byte Spill
 ; CHECK-NEXT:    vmov r3, s1
 ; CHECK-NEXT:    vmovx.f16 s0, s2
 ; CHECK-NEXT:    vmov.16 q3[2], r3
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #80] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q3[3], r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    vmov.16 q3[4], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmovx.f16 s0, s10
 ; CHECK-NEXT:    vmov.16 q3[5], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmovx.f16 s0, s18
 ; CHECK-NEXT:    vmov r3, s0
 ; CHECK-NEXT:    vmov.16 q1[0], r2
 ; CHECK-NEXT:    vmov.16 q1[1], r3
 ; CHECK-NEXT:    vmov r2, s11
 ; CHECK-NEXT:    vmovx.f16 s0, s11
 ; CHECK-NEXT:    vmov.16 q1[3], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmovx.f16 s0, s19
 ; CHECK-NEXT:    vmov.16 q1[6], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmov.16 q1[7], r2
-; CHECK-NEXT:    vstrw.32 q3, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT:    vmov.32 r3, q5[3]
 ; CHECK-NEXT:    vmov.f32 s6, s19
 ; CHECK-NEXT:    vmovx.f16 s0, s5
-; CHECK-NEXT:    vstrw.32 q4, [sp, #48] @ 16-byte Spill
-; CHECK-NEXT:    vstrw.32 q1, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT:    vmov.32 r3, q5[3]
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vdup.32 q0, r3
-; CHECK-NEXT:    vldrw.u32 q5, [r0, #16]
 ; CHECK-NEXT:    vmov r3, s1
 ; CHECK-NEXT:    vmovx.f16 s0, s2
 ; CHECK-NEXT:    vmov.16 q2[2], r3
-; CHECK-NEXT:    vmov r3, s20
+; CHECK-NEXT:    vldrw.u32 q5, [r0, #16]
 ; CHECK-NEXT:    vmov.16 q2[3], r2
+; CHECK-NEXT:    vstrw.32 q3, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT:    vmov r3, s20
+; CHECK-NEXT:    vldrw.u32 q3, [r0, #80]
 ; CHECK-NEXT:    vmov.16 q7[0], r3
+; CHECK-NEXT:    vstrw.32 q1, [sp, #96] @ 16-byte Spill
 ; CHECK-NEXT:    vmov r2, s6
-; CHECK-NEXT:    vldrw.u32 q3, [r0, #80]
+; CHECK-NEXT:    vstrw.32 q4, [sp, #48] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.16 q2[4], r2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmov.16 q2[5], r2
 ; CHECK-NEXT:    vstrw.32 q2, [sp, #64] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #48]
 ; CHECK-NEXT:    vmov.32 r0, q3[0]
 ; CHECK-NEXT:    vmov r2, s8
 ; CHECK-NEXT:    vmovx.f16 s0, s8

llvm/unittests/Target/ARM/MachineInstrTest.cpp

for (auto &Op : Desc.operands()) {
                 << ": mismatched expectation for tail-predicated safety\n";
       break;
     }
   }
 }
 
 TEST(MachineInstr, HasSideEffects) {
   using namespace ARM;
-  unsigned Opcodes[] = {
-      // MVE Loads/Stores
-      MVE_VLDRBS16,        MVE_VLDRBS16_post,   MVE_VLDRBS16_pre,
-      MVE_VLDRBS16_rq,     MVE_VLDRBS32,        MVE_VLDRBS32_post,
-      MVE_VLDRBS32_pre,    MVE_VLDRBS32_rq,     MVE_VLDRBU16,
-      MVE_VLDRBU16_post,   MVE_VLDRBU16_pre,    MVE_VLDRBU16_rq,
-      MVE_VLDRBU32,        MVE_VLDRBU32_post,   MVE_VLDRBU32_pre,
-      MVE_VLDRBU32_rq,     MVE_VLDRBU8,         MVE_VLDRBU8_post,
-      MVE_VLDRBU8_pre,     MVE_VLDRBU8_rq,      MVE_VLDRDU64_qi,
-      MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq,     MVE_VLDRDU64_rq_u,
-      MVE_VLDRHS32,        MVE_VLDRHS32_post,   MVE_VLDRHS32_pre,
-      MVE_VLDRHS32_rq,     MVE_VLDRHS32_rq_u,   MVE_VLDRHU16,
-      MVE_VLDRHU16_post,   MVE_VLDRHU16_pre,    MVE_VLDRHU16_rq,
-      MVE_VLDRHU16_rq_u,   MVE_VLDRHU32,        MVE_VLDRHU32_post,
-      MVE_VLDRHU32_pre,    MVE_VLDRHU32_rq,     MVE_VLDRHU32_rq_u,
-      MVE_VLDRWU32,        MVE_VLDRWU32_post,   MVE_VLDRWU32_pre,
-      MVE_VLDRWU32_qi,     MVE_VLDRWU32_qi_pre, MVE_VLDRWU32_rq,
-      MVE_VLDRWU32_rq_u,   MVE_VLD20_16,        MVE_VLD20_16_wb,
-      MVE_VLD20_32,        MVE_VLD20_32_wb,     MVE_VLD20_8,
-      MVE_VLD20_8_wb,      MVE_VLD21_16,        MVE_VLD21_16_wb,
-      MVE_VLD21_32,        MVE_VLD21_32_wb,     MVE_VLD21_8,
-      MVE_VLD21_8_wb,      MVE_VLD40_16,        MVE_VLD40_16_wb,
-      MVE_VLD40_32,        MVE_VLD40_32_wb,     MVE_VLD40_8,
-      MVE_VLD40_8_wb,      MVE_VLD41_16,        MVE_VLD41_16_wb,
-      MVE_VLD41_32,        MVE_VLD41_32_wb,     MVE_VLD41_8,
-      MVE_VLD41_8_wb,      MVE_VLD42_16,        MVE_VLD42_16_wb,
-      MVE_VLD42_32,        MVE_VLD42_32_wb,     MVE_VLD42_8,
-      MVE_VLD42_8_wb,      MVE_VLD43_16,        MVE_VLD43_16_wb,
-      MVE_VLD43_32,        MVE_VLD43_32_wb,     MVE_VLD43_8,
-      MVE_VLD43_8_wb,      MVE_VSTRB16,         MVE_VSTRB16_post,
-      MVE_VSTRB16_pre,     MVE_VSTRB16_rq,      MVE_VSTRB32,
-      MVE_VSTRB32_post,    MVE_VSTRB32_pre,     MVE_VSTRB32_rq,
-      MVE_VSTRB8_rq,       MVE_VSTRBU8,         MVE_VSTRBU8_post,
-      MVE_VSTRBU8_pre,     MVE_VSTRD64_qi,      MVE_VSTRD64_qi_pre,
-      MVE_VSTRD64_rq,      MVE_VSTRD64_rq_u,    MVE_VSTRH16_rq,
-      MVE_VSTRH16_rq_u,    MVE_VSTRH32,         MVE_VSTRH32_post,
-      MVE_VSTRH32_pre,     MVE_VSTRH32_rq,      MVE_VSTRH32_rq_u,
-      MVE_VSTRHU16,        MVE_VSTRHU16_post,   MVE_VSTRHU16_pre,
-      MVE_VSTRW32_qi,      MVE_VSTRW32_qi_pre,  MVE_VSTRW32_rq,
-      MVE_VSTRW32_rq_u,    MVE_VSTRWU32,        MVE_VSTRWU32_post,
-      MVE_VSTRWU32_pre,    MVE_VST20_16,        MVE_VST20_16_wb,
-      MVE_VST20_32,        MVE_VST20_32_wb,     MVE_VST20_8,
-      MVE_VST20_8_wb,      MVE_VST21_16,        MVE_VST21_16_wb,
-      MVE_VST21_32,        MVE_VST21_32_wb,     MVE_VST21_8,
-      MVE_VST21_8_wb,      MVE_VST40_16,        MVE_VST40_16_wb,
-      MVE_VST40_32,        MVE_VST40_32_wb,     MVE_VST40_8,
-      MVE_VST40_8_wb,      MVE_VST41_16,        MVE_VST41_16_wb,
-      MVE_VST41_32,        MVE_VST41_32_wb,     MVE_VST41_8,
-      MVE_VST41_8_wb,      MVE_VST42_16,        MVE_VST42_16_wb,
-      MVE_VST42_32,        MVE_VST42_32_wb,     MVE_VST42_8,
-      MVE_VST42_8_wb,      MVE_VST43_16,        MVE_VST43_16_wb,
-      MVE_VST43_32,        MVE_VST43_32_wb,     MVE_VST43_8,
-      MVE_VST43_8_wb,
+  std::set<unsigned> UnpredictableOpcodes = {
+      MVE_VCTP8,     MVE_VCTP16,    MVE_VCTP32,    MVE_VCTP64,    MVE_VPST,
+      MVE_VPTv16i8,  MVE_VPTv8i16,  MVE_VPTv4i32,  MVE_VPTv16i8r, MVE_VPTv8i16r,
+      MVE_VPTv4i32r, MVE_VPTv16s8,  MVE_VPTv8s16,  MVE_VPTv4s32,  MVE_VPTv16s8r,
+      MVE_VPTv8s16r, MVE_VPTv4s32r, MVE_VPTv16u8,  MVE_VPTv8u16,  MVE_VPTv4u32,
+      MVE_VPTv16u8r, MVE_VPTv8u16r, MVE_VPTv4u32r, MVE_VPTv8f16,  MVE_VPTv4f32,
+      MVE_VPTv8f16r, MVE_VPTv4f32r, MVE_VADC,      MVE_VADCI,     MVE_VSBC,
+      MVE_VSBCI,     MVE_VSHLC,
   };
 
   LLVMInitializeARMTargetInfo();
   LLVMInitializeARMTarget();
   LLVMInitializeARMTargetMC();
 
   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
   std::string Error;
   const Target *T = TargetRegistry::lookupTarget(TT, Error);
   if (!T) {
     dbgs() << Error;
     return;
   }
 
   TargetOptions Options;
   auto TM = std::unique_ptr<LLVMTargetMachine>(
       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
                   std::string(TM->getTargetFeatureString()),
                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
   auto MII = TM->getMCInstrInfo();
 
-  for (unsigned Op : Opcodes) {
+  for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
     const MCInstrDesc &Desc = TII->get(Op);
+    if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE)
+      continue;
+    if (UnpredictableOpcodes.count(Op))
+      continue;
+
     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
         << MII->getName(Op) << " has unexpected side effects";
   }
 }