[PPCInstPrinter] Print conditional branches as `bt 2, $target` instead of `bt 2, .+$imm`

[MaskRay]

Summary

Follow-up of D76591.

[jhenderson]

I'm out of my depth here, so can't realistically review this. Sorry.

I did see that the harbourmaster tests failed though. Are they related?

[MaskRay]

Fix lld/ELF/ppc* tests

[MaskRay]

In D76907#1949346, @jhenderson wrote:

I'm out of my depth here, so can't realistically review this. Sorry.

I did see that the harbourmaster tests failed though. Are they related?

lld/test/ELF/ppc* need fixing. Since there were not many, I just fixed them. I worried people may have different ideas on the output.

[sfertile]

1 comment, but otherwise LGTM.

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

63

Minor nit: Maybe decodeCondBrTarget since condition branches have other operands.

[MaskRay]

Change decodeCondBrOperand to decodeCondBrTarget

lld/test/ELF/ppc32-call-stub-pic.s

 # RELOC-NEXT:   R_PPC_JMP_SLOT h 0x0
 # RELOC-NEXT: }
 
 # SEC: .got PROGBITS 00020368
 # DYN: PPC_GOT 0x20368
 
 ## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764
 # CHECK-LABEL: <_start>:
-# CHECK-NEXT:         bcl 20, 31, .+4
+# PIE-NEXT:           bcl 20, 31, 0x10210
 # PIE-NEXT:    10210: mflr 30
 # PIE-NEXT:           addis 30, 30, 3
 # PIE-NEXT:           addi 30, 30, -32412
 ## Two bl 00008000.got2.plt_pic32.f
 # PIE-NEXT:           bl 0x10244
 # PIE-NEXT:           bl 0x10244
 ## Two bl 00008000.got2.plt_pic32.g
 # PIE-NEXT:           bl 0x10254
 # PIE-NEXT:           bl 0x10254
 ## Two bl 00008000.got2.plt_pic32.h
 # PIE-NEXT:           bl 0x10264
 # PIE-NEXT:           bl 0x10264
 # PIE-NEXT:           addis 30, 30, {{.*}}
 # PIE-NEXT:           addi 30, 30, {{.*}}
 ## bl 00008000.plt_pic32.f
 # PIE-NEXT:           bl 0x10274
 ## bl 00008000.plt_pic32.f
 # PIE-NEXT:           bl 0x10284
+# SHARED-NEXT:        bcl 20, 31, 0x10230
 # SHARED-NEXT: 10230: mflr 30
 # SHARED-NEXT:        addis 30, 30, 3
 # SHARED-NEXT:        addi 30, 30, -32420
 # SHARED-NEXT:        bl 0x10264
 # SHARED-NEXT:        bl 0x10264
 # SHARED-NEXT:        bl 0x10274
 # SHARED-NEXT:        bl 0x10274
 # SHARED-NEXT:        bl 0x10284

 # CHECK-NEXT: b .+12
 # CHECK-NEXT: b .+8
 # CHECK-NEXT: b .+4
 
 ## PLTresolve
 ## Operand of addi: 0x100a8-.glink = 24
 # CHECK-NEXT:         addis 11, 11, 0
 # CHECK-NEXT:         mflr 0
-# CHECK-NEXT:         bcl 20, 31, .+4
-# PIE-NEXT:    102ac: addi 11, 11, 24
-# SHARED-NEXT: 102cc: addi 11, 11, 24
+# CHECK-NEXT:         bcl 20, 31, 0x[[#%x,NEXT:]]
+# CHECK-NEXT: [[#%x,NEXT]]: addi 11, 11, 24
 
 # CHECK-NEXT: mflr 12
 # CHECK-NEXT: mtlr 0
 # CHECK-NEXT: subf 11, 12, 11
 
 ## Operand of lwz in -pie mode: &.got[1] - 0x100a8 = 0x20088+4 - 0x100a8 = 65536*1-28
 # CHECK-NEXT:  addis 12, 12, 1
 # PIE-NEXT:    lwz 0, 192(12)

lld/test/ELF/ppc32-long-thunk.s

 # PD-NEXT:        2028: lis 12, 512
 # PD-NEXT:              addi 12, 12, 8208
 # PD-NEXT:              mtctr 12
 # PD-NEXT:              bctr
 
 ## high-0x2028 = 0x02002008-0x2020 = 65536*512-24
 # PI:         <__LongThunk_high>:
 # PI-NEXT:        2018: mflr 0
-# PI-NEXT:              bcl 20, 31, .+4
+# PI-NEXT:              bcl 20, 31, 0x2020
 # PI-NEXT:        2020: mflr 12
 # PI-NEXT:              addis 12, 12, 512
 # PI-NEXT:              addi 12, 12, -24
 # PI-NEXT:              mtlr 0
 # PI-NEXT:              mtctr 12
 # PI-NEXT:              bctr
 
 ## .text_high+16-0x2048 = 0x02002010-0x2048 = 65536*512-48
 # PI:         <__LongThunk_>:
 # PI-NEXT:        2038: mflr 0
-# PI-NEXT:              bcl 20, 31, .+4
+# PI-NEXT:              bcl 20, 31, 0x2040
 # PI-NEXT:        2040: mflr 12
 # PI-NEXT:              addis 12, 12, 512
 # PI-NEXT:              addi 12, 12, -48
 # PI-NEXT:              mtlr 0
 # PI-NEXT:              mtctr 12
 # PI-NEXT:              bctr
 
 .section .text_low, "ax", %progbits

lld/test/ELF/ppc32-reloc-rel.s

 # REQUIRES: ppc
 # RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
 # RUN: ld.lld %t.o -o %t
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 
 .section .R_PPC_REL14,"ax",@progbits
   beq 1f
 1:
 # CHECK-LABEL: section .R_PPC_REL14:
-# CHECK: bt 2, .+4
+# CHECK: 100100b4: bt 2, 0x100100b8
 
 .section .R_PPC_REL24,"ax",@progbits
   b 1f
 1:
 # CHECK-LABEL: section .R_PPC_REL24:
 # CHECK: b .+4
 
 .section .R_PPC_REL32,"ax",@progbits

lld/test/ELF/ppc64-reloc-rel.s

 # REQUIRES: ppc
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o
 # RUN: ld.lld %t.o --defsym=foo=rel16+0x8000 -o %t
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 # RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=REL %s
 # RUN: llvm-readelf -S %t | FileCheck --check-prefix=SEC %s
 # RUN: llvm-readelf -x .eh_frame %t | FileCheck --check-prefix=HEX %s
 
 .section .R_PPC64_REL14,"ax",@progbits
 # FIXME This does not produce a relocation
   beq 1f
 1:
 # CHECK-LABEL: Disassembly of section .R_PPC64_REL14:
-# CHECK: bt 2, .+4
+# CHECK: bt 2, 0x10010198
 
 .section .R_PPC64_REL16,"ax",@progbits
 .globl rel16
 rel16:
   li 3, foo-rel16-1@ha      # R_PPC64_REL16_HA
   li 3, foo-rel16@ha
   li 4, foo-rel16+0x7fff@h  # R_PPC64_REL16_HI
   li 4, foo-rel16+0x8000@h

lld/test/ELF/ppc64-split-stack-adjust-overflow.s

.Lcaller_alloc_more:
     b .Lcaller_body
         .size caller, .-caller
 
 # CHECK-LABEL: caller
 # CHECK:      ld 0, -28736(13)
 # CHECK-NEXT: addis 12, 1, -32768
 # CHECK-NEXT: nop
 # CHECK-NEXT: cmpld 7, 12, 0
-# CHECK-NEXT: bt- 28, .+36
+# CHECK-NEXT: bt- 28, 0x10010204
 
 .section        .note.GNU-split-stack,"",@progbits

lld/test/ELF/ppc64-split-stack-adjust-size-success.s

.Lcaller_alloc_more:
     b .Lcaller_body
         .size caller, .-caller
 
 # CHECK-LABEL: caller
 # CHECK:      ld 0, -28736(13)
 # CHECK-NEXT: addis 12, 1, -1
 # CHECK-NEXT: addi 12, 12, 32736
 # CHECK-NEXT: cmpld 7, 12, 0
-# CHECK-NEXT: bt- 28, .+36
+# CHECK-NEXT: bt- 28, 0x10010204
 
 # SMALL-LABEL: caller
 # SMALL:      ld 0, -28736(13)
 # SMALL-NEXT: addi 12, 1, -4128
 # SMALL-NEXT: nop
 # SMALL-NEXT: cmpld 7, 12, 0
-# SMALL-NEXT: bt- 28, .+36
+# SMALL-NEXT: bt- 28, 0x10010204
 
 # ZERO-LABEL: caller
 # ZERO:      ld 0, -28736(13)
 # ZERO-NEXT: addi 12, 1, -32
 # ZERO-NEXT: nop
 # ZERO-NEXT: cmpld 7, 12, 0
-# ZERO-NEXT: bt- 28, .+36
+# ZERO-NEXT: bt- 28, 0x10010204
         .p2align    2
         .global main
   .type  main, @function
 main:
 .Lmain_gep:
     addis 2,12,.TOC.-.Lmain_gep@ha
     addi 2,2,.TOC.-.Lmain_gep@l
     .localentry main,.-main

lld/test/ELF/ppc64-split-stack-prologue-adjust-success.s

.Lcss_alloc_more:
     b .Lcss_body
         .size caller_small_stack, .-caller_small_stack
 
 # CHECK-LABEL: caller_small_stack
 # CHECK:       ld 0, -28736(13)
 # CHECK-NEXT:  addi 12, 1, -16416
 # CHECK-NEXT:  nop
 # CHECK-NEXT:  cmpld 7, 12, 0
-# CHECK-NEXT:  bt-  28, .+36
+# CHECK-NEXT:  bt-  28, 0x10010204
 
 # A caller that has a stack size that fits whithin 16 bits, but the adjusted
 # stack size after prologue adjustment now overflows 16 bits needing both addis
 # and addi instructions.
         .p2align    2
         .global caller_med_stack
         .type caller_med_stack, @function
 caller_med_stack:
.Lcls_alloc_more:
     b .Lcls_body
         .size caller_large_stack, .-caller_large_stack
 
 # CHECK-LABEL: caller_large_stack
 # CHECK:       ld 0, -28736(13)
 # CHECK-NEXT:  addis 12, 1, -1
 # CHECK-NEXT:  addi 12, 12, -16416
 # CHECK-NEXT:  cmpld 7, 12, 0
-# CHECK-NEXT:  bt-  28, .+44
+# CHECK-NEXT:  bt-  28, 0x100102bc
 
 # A caller with a stack size that is larger then 16 bits, but aligned such that
 # the addi instruction is unneeded.
         .p2align    2
         .global caller_large_aligned_stack
         .type caller_large_aligned_stack, @function
 caller_large_aligned_stack:
 .Lclas_gep:
.Lclas_alloc_more:
     b .Lclas_body
         .size caller_large_aligned_stack, .-caller_large_aligned_stack
 
 # CHECK-LABEL: caller_large_aligned_stack
 # CHECK:       ld 0, -28736(13)
 # CHECK-NEXT:  addis 12, 1, -2
 # CHECK-NEXT:  addi 12, 12, -16384
 # CHECK-NEXT:  cmpld 7, 12, 0
-# CHECK-NEXT:  bt-  28, .+40
+# CHECK-NEXT:  bt-  28, 0x10010318
 
 # main only calls split-stack functions or __morestack so
 # there should be no adjustment of its split-stack prologue.
         .p2align    2
         .global main
   .type  main, @function
 main:
 .Lmain_gep:

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
                                          createPPCDisassembler);
   TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
                                          createPPCDisassembler);
   TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
                                          createPPCLEDisassembler);
 }
 
+static DecodeStatus decodeCondBrOperand(MCInst &Inst, unsigned Imm,
+                                        uint64_t /*Address*/,
+                                        const void * /*Decoder*/) {
+  Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm,
                                               uint64_t Addr,
                                               const void *Decoder) {
   int32_t Offset = SignExtend32<24>(Imm);
   Inst.addOperand(MCOperand::createImm(Offset));
   return MCDisassembler::Success;
 }
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }
 def PPCCondBrAsmOperand : AsmOperandClass {
   let Name = "CondBr"; let PredicateMethod = "isCondBr";
   let RenderMethod = "addBranchTargetOperands";
 }
 def condbrtarget : Operand<OtherVT> {
   let PrintMethod = "printBranchOperand";
   let EncoderMethod = "getCondBrEncoding";
+  let DecoderMethod = "decodeCondBrOperand";
   let ParserMatchClass = PPCCondBrAsmOperand;
+  let OperandType = "OPERAND_PCREL";
 }
 def abscondbrtarget : Operand<OtherVT> {
   let PrintMethod = "printAbsBranchOperand";
   let EncoderMethod = "getAbsCondBrEncoding";
   let ParserMatchClass = PPCCondBrAsmOperand;
 }
 def calltarget : Operand<iPTR> {
   let PrintMethod = "printBranchOperand";

llvm/test/CodeGen/PowerPC/aix-return55.ll

 ;CHECKOBJ-NEXT:       8: 68 65 6c 6c                   xori 5, 3, 27756
 ;CHECKOBJ-NEXT:       c: 6f 77 6f 72 xoris 23, 27, 28530
 ;CHECKOBJ-NEXT:      10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: Disassembly of section .data:{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: 00000018 <a>:
 ;CHECKOBJ-NEXT:      18: 00 01 23 45                   <unknown>
 ;CHECKOBJ-NEXT:      1c: 67 8a bc de                   oris 10, 28, 48350{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: 00000020 <d>:
-;CHECKOBJ-NEXT:      20: 40 14 00 00                   bdnzf   20, .+0
+;CHECKOBJ-NEXT:      20: 40 14 00 00                   bdnzf   20, 0x20
 ;CHECKOBJ-NEXT:      24: 00 00 00 00                   <unknown>{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: 00000028 <foo>:
 ;CHECKOBJ-NEXT:      28: 00 00 00 00                   <unknown>
 ;CHECKOBJ-NEXT:      2c: 00 00 00 34                   <unknown>
 ;CHECKOBJ-NEXT:      30: 00 00 00 00                   <unknown>
 
 ;CHECKSECT: Sections [
 ;CHECKSECT-NEXT:   Section {

llvm/test/CodeGen/PowerPC/alignlongjumptest.mir

bb.1:
     renamable $x3 = LI8 1
     INLINEASM &".space 32744", 1
     renamable $x3 = PADDI8 $x3, 21
     BLR8 implicit $lr8, implicit $rm, implicit killed $x3
 
 ...
 
 # Check for the long branch.
-# CHECK-LE:         08 00 82 4{{[01]}}   b{{[tf]}}  2, .+8
+# CHECK-LE:         08 00 82 4{{[01]}}   b{{[tf]}}  2, 0xc
 # CHECK-LE-NEXT:    fc 7f 00 48   b .+32764
 # CHECK-LE-DAG:     paddi 3, 3, 13, 0
 # CHECK-LE-DAG:     paddi 3, 3, 21, 0
 # CHECK-LE:         blr
-# CHECK-BE:         4{{[01]}} 82 00 08   b{{[tf]}}  2, .+8
+# CHECK-BE:         4{{[01]}} 82 00 08   b{{[tf]}}  2, 0xc
 # CHECK-BE-NEXT:    48 00 7f fc   b .+32764
 # CHECK-BE-DAG:     paddi 3, 3, 13, 0
 # CHECK-BE-DAG:     paddi 3, 3, 21, 0
 # CHECK-BE:         blr
 
 

llvm/test/MC/PowerPC/ppc64-prefix-align.s

 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --filetype=obj -o - %s | \
 # RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --filetype=obj -o - %s | \
 # RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-LE %s
 
 # The purpose of this test is to make sure that 8 byte instructions do not
 # cross 64 byte boundaries. If an 8 byte instruction is about to cross such
 # a boundary then a nop should be added so that the 8 byte instruction starts
 # 4 bytes later and does not cross the boundary.
 # This instruction is 8 bytes: paddi 1, 2, 8589934576, 0
 # This instruction is 4 bytes: addi 2, 3, 15
 # The branches are also 4 bytes each: beq 0, LAB1 (or LAB2)
 
 beq 0, LAB1               # 4
 beq 1, LAB2               # 8
-# CHECK-BE:       0: 41 82 00 c0        bt 2, .+192
-# CHECK-BE-NEXT:  4: 41 86 00 f8        bt 6, .+248
-# CHECK-LE:       0: c0 00 82 41        bt 2, .+192
-# CHECK-LE-NEXT:  4: f8 00 86 41        bt 6, .+248
+# CHECK-BE:       0: 41 82 00 c0        bt 2, 0xc0
+# CHECK-BE-NEXT:  4: 41 86 00 f8        bt 6, 0xfc
+# CHECK-LE:       0: c0 00 82 41        bt 2, 0xc0
+# CHECK-LE-NEXT:  4: f8 00 86 41        bt 6, 0xfc
 paddi 1, 2, 8589934576, 0 # 16
 paddi 1, 2, 8589934576, 0 # 24
 paddi 1, 2, 8589934576, 0 # 32
 paddi 1, 2, 8589934576, 0 # 40
 paddi 1, 2, 8589934576, 0 # 48
 paddi 1, 2, 8589934576, 0 # 56
 addi 2, 3, 15             # 60
 # Below the lines 40: and 44: contain the 8 byte instruction.

llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s

 # CHECK-NEXT:   b .+4
 
 b:
   b .-4
   b .
   b .+4
 
 # CHECK-LABEL: <bt>:
-# CHECK-NEXT:   bt 2, .+65532
+# CHECK-NEXT:   18: bt 2, 0x14
+# CHECK-NEXT:   1c: bt 1, 0x20
 
 bt:
   bt 2, .-4
+  bgt .+4

llvm/test/tools/llvm-objdump/XCOFF/disassemble-all.test

 CHECK-NEXT:       9c: 00 00 00 00                   <unknown>
 CHECK:        000000a0 <b>:
 CHECK-NEXT:       a0: 00 00 30 39                   <unknown>
 CHECK:        Disassembly of section .bss:
 CHECK:        000000a4 <a>:
 CHECK-NEXT:        ...
 CHECK:        Disassembly of section .tdata:
 CHECK:        00000000 <d>:
-CHECK-NEXT:        0: 40 09 21 f9                   bdnzfl  9, .+8696
+CHECK-NEXT:        0: 40 09 21 f9                   bdnzfl  9, 0x21f8
 CHECK-NEXT:        4: f0 1b 86 6e                   <unknown>
 CHECK:        Disassembly of section .tbss:
 CHECK:        00000008 <c>:
 CHECK-NEXT:        ...