This is an archive of the discontinued LLVM Phabricator instance.

Differential D76841

[ARM] Fix MVE VCMPr f16 pattern
ClosedPublic

Authored by dmgreen on Mar 26 2020, 6:07 AM.

Details

Reviewers
SjoerdMeijer
samparker
simon_tatham
Pierre-vh
Commits
rG8689f98e9ba5: [ARM] Fix MVE VCMPr f16 pattern
Summary

This patterns seemed to be using the f32 instruction, not f16. Fix it to use the correct one.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 26 2020, 6:07 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptMar 26 2020, 6:07 AM
SjoerdMeijer accepted this revision.Mar 26 2020, 6:34 AM

2-character changes that fix wrong codegen are always good changes, so have no problem directly LGTM'ing this.

This revision is now accepted and ready to land.Mar 26 2020, 6:34 AM
Closed by commit rG8689f98e9ba5: [ARM] Fix MVE VCMPr f16 pattern (authored by dmgreen). · Explain WhyMar 27 2020, 4:19 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMar 27 2020, 4:19 AM

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
test/
CodeGen/
Thumb2/
16 lines

Diff 253077

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,095 Lines • ▼ Show 20 Lines
multiclass unpred_vcmpf_z<PatLeaf fc> { multiclass unpred_vcmpf_z<PatLeaf fc> {
def f16 : Pat<(v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)), def f16 : Pat<(v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)), def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)))),
(v8i1 (MVE_VCMPf32r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
} }
multiclass unpred_vcmpf_r<int fc> { multiclass unpred_vcmpf_r<int fc> {
def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)), def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)),
(v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>; (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>;
def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)), def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)),
▲ Show 20 Lines • Show All 2,915 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

Show First 20 Lines • Show All 1,004 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpnot ; CHECK-MVEFP-NEXT: vpnot
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> %src, zeroinitializer %c = fcmp one <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 601 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> %src, zeroinitializer %c = fcmp ueq <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 708 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpnot ; CHECK-MVEFP-NEXT: vpnot
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> %src, zeroinitializer %c = fcmp ord <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> %src, zeroinitializer %c = fcmp uno <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 1,003 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpnot ; CHECK-MVEFP-NEXT: vpnot
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> zeroinitializer, %src %c = fcmp one <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 601 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> zeroinitializer, %src %c = fcmp ueq <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 708 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpnot ; CHECK-MVEFP-NEXT: vpnot
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> zeroinitializer, %src %c = fcmp ord <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> zeroinitializer, %src %c = fcmp uno <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }