[InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors

[jroelofs]

Summary

Fixes https://bugs.llvm.org/show_bug.cgi?id=43665

[lebedev.ri]

What we need to do here is "define" undef to be 0.

----------------------------------------
define <4 x i5> @test_v4i5_not_ashr_negative_const_undef(<4 x i5> %a0) {
%0:
  %1 = ashr <4 x i5> { 29, 27, undef, 23 }, %a0
  %2 = xor <4 x i5> { 31, 31, 31, undef }, %1
  ret <4 x i5> %2
}
=>
define <4 x i5> @test_v4i5_not_ashr_negative_const_undef(<4 x i5> %a0) {
%0:
  %1 = lshr <4 x i5> { 2, 4, 0, 8 }, %a0
  ret <4 x i5> %1
}
Transformation seems to be correct!

Summary:
  1 correct transformations
  0 incorrect transformations
  0 Alive2 errors

There was some utility for that already, but i don't recall how it's called..

[spatel]

In D76800#1942204, @lebedev.ri wrote:

What we need to do here is "define" undef to be 0.

----------------------------------------
define <4 x i5> @test_v4i5_not_ashr_negative_const_undef(<4 x i5> %a0) {
%0:
  %1 = ashr <4 x i5> { 29, 27, undef, 23 }, %a0
  %2 = xor <4 x i5> { 31, 31, 31, undef }, %1
  ret <4 x i5> %2
}
=>
define <4 x i5> @test_v4i5_not_ashr_negative_const_undef(<4 x i5> %a0) {
%0:
  %1 = lshr <4 x i5> { 2, 4, 0, 8 }, %a0
  ret <4 x i5> %1
}
Transformation seems to be correct!

Summary:
  1 correct transformations
  0 incorrect transformations
  0 Alive2 errors

There was some utility for that already, but i don't recall how it's called..

Probably want this:

/// Some binary operators require special handling to avoid poison and undefined
/// behavior. If a constant vector has undef elements, replace those undefs with
/// identity constants if possible because those are always safe to execute.
/// If no identity constant exists, replace undef with some other safe constant.
static inline Constant *getSafeVectorConstantForBinop()

[RKSimon]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

3072

m_Negative uses cst_pred_ty internally which just continues if it finds an undef in a vector - maybe we don't want that?

[lebedev.ri]

In D76800#1942223, @spatel wrote:

static inline Constant *getSafeVectorConstantForBinop()

Yes, i think that's the one.

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

3072

We only need to handle undefs correctly, we don't need to completely give up on them here.

[jroelofs]

Implement review feedback

[lebedev.ri]

LG, thank you.

[jroelofs]

https://github.com/llvm/llvm-project/commit/7a89a5d81bbdc0ab6dbd14d9af4a52e64c868423

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

     // If we are inverting a right-shifted constant, we may be able to eliminate
     // the 'not' by inverting the constant and using the opposite shift type.
     // Canonicalization rules ensure that only a negative constant uses 'ashr',
     // but we must check that in case that transform has not fired yet.
 
     // ~(C >>s Y) --> ~C >>u Y (when inverting the replicated sign bits)
     Constant *C;
     if (match(NotVal, m_AShr(m_Constant(C), m_Value(Y))) &&
-        match(C, m_Negative()))
+        match(C, m_Negative()) &&
+        (!C->getType()->isVectorTy() || !C->containsUndefElement()))
       return BinaryOperator::CreateLShr(ConstantExpr::getNot(C), Y);
 
     // ~(C >>u Y) --> ~C >>s Y (when inverting the replicated sign bits)
     if (match(NotVal, m_LShr(m_Constant(C), m_Value(Y))) &&
         match(C, m_NonNegative()))
       return BinaryOperator::CreateAShr(ConstantExpr::getNot(C), Y);
 
     // ~(X + C) --> -(C + 1) - X

llvm/test/Transforms/InstCombine/vector-xor.ll

 ;
   %1 = ashr <4 x i32> <i32 -3, i32 -5, i32 -7, i32 -9>, %a0
   %2 = xor  <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %1
   ret <4 x i32> %2
 }
 
 define <4 x i32> @test_v4i32_not_ashr_negative_const_undef(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_not_ashr_negative_const_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> <i32 2, i32 4, i32 undef, i32 8>, [[A0:%.*]]
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> <i32 -3, i32 -5, i32 undef, i32 -9>, [[A0:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], <i32 -1, i32 -1, i32 -1, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = ashr <4 x i32> <i32 -3, i32 -5, i32 undef, i32 -9>, %a0
   %2 = xor  <4 x i32> <i32 -1, i32 -1, i32 -1, i32 undef>, %1
   ret <4 x i32> %2
 }
 
 ; ~(C >>u Y) --> ~C >>s Y (when inverting the replicated sign bits)