[ARM] Fix incorrect handling of big-endian vmov.i64

[john.brawn]

Summary

Currently when the target is big-endian vmov.i64 reverses the order of the two words of the vector. This is correct only when the underlying element type is 32-bit, as actually what it should be doing is considering it a vector of the underlying type and reversing the elements of that.

[john.brawn]

Apply clang-format changes.

[dmgreen]

Amazing. I was going to say I'm not surprised we get big endian wrong. But it's a movimm. I am a little surprised.

As I've said before, I like the test update script for it's consistency and the fact it doesn't hide any instructions.

Results look better. LGTM.

[john.brawn]

Rebase.

llvm/lib/Target/ARM/ARMISelLowering.cpp

return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
                      CCR, Chain.getValue(1));
 }
 
 /// isVMOVModifiedImm - Check if the specified splat value corresponds to a
 /// valid vector constant for a NEON or MVE instruction with a "modified
 /// immediate" operand (e.g., VMOV).  If so, return the encoded value.
 static SDValue isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
                                  unsigned SplatBitSize, SelectionDAG &DAG,
-                                 const SDLoc &dl, EVT &VT, bool is128Bits,
+                                 const SDLoc &dl, EVT &VT, EVT VectorVT,
                                  VMOVModImmType type) {
   unsigned OpCmode, Imm;
+  bool is128Bits = VectorVT.is128BitVector();
 
   // SplatBitSize is set to the smallest size that splats the vector, so a
   // zero vector will always have SplatBitSize == 8.  However, NEON modified
   // immediate instructions others than VMOV do not support the 8-bit encoding
   // of a zero vector, and the default encoding of zero is supposed to be the
   // 32-bit version.
   if (SplatBits == 0)
     SplatBitSize = 32;
for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
         Imm |= ImmMask;
       } else if ((SplatBits & BitMask) != 0) {
         return SDValue();
       }
       BitMask <<= 8;
       ImmMask <<= 1;
     }
 
-    if (DAG.getDataLayout().isBigEndian())
-      // swap higher and lower 32 bit word
-      Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
+    if (DAG.getDataLayout().isBigEndian()) {
+      // Reverse the order of elements within the vector.
+      unsigned BytesPerElem = VectorVT.getScalarSizeInBits() / 8;
+      unsigned Mask = (1 << BytesPerElem) - 1;
+      unsigned NumElems = 8 / BytesPerElem;
+      unsigned NewImm = 0;
+      for (unsigned ElemNum = 0; ElemNum < NumElems; ++ElemNum) {
+        unsigned Elem = ((Imm >> ElemNum * BytesPerElem) & Mask);
+        NewImm |= Elem << (NumElems - ElemNum - 1) * BytesPerElem;
+      }
+      Imm = NewImm;
+    }
 
     // Op=1, Cmode=1110.
     OpCmode = 0x1e;
     VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
     break;
   }
 
   default:
SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
   // It wouldn't really be worth bothering for doubles except for one very
   // important value, which does happen to match: 0.0. So make sure we don't do
   // anything stupid.
   if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
     return SDValue();
 
   // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
   SDValue NewVal = isVMOVModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
-                                     VMovVT, false, VMOVModImm);
+                                     VMovVT, VT, VMOVModImm);
   if (NewVal != SDValue()) {
     SDLoc DL(Op);
     SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
                                       NewVal);
     if (IsDouble)
       return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
 
     // It's a float: cast and extract a vector element.
     SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
                                        VecConstant);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
                        DAG.getConstant(0, DL, MVT::i32));
   }
 
   // Finally, try a VMVN.i32
   NewVal = isVMOVModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
-                             false, VMVNModImm);
+                             VT, VMVNModImm);
   if (NewVal != SDValue()) {
     SDLoc DL(Op);
     SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
 
     if (IsDouble)
       return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
 
     // It's a float: cast and extract a vector element.
SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
   if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
     if (SplatUndef.isAllOnesValue())
       return DAG.getUNDEF(VT);
 
     if ((ST->hasNEON() && SplatBitSize <= 64) ||
         (ST->hasMVEIntegerOps() && SplatBitSize <= 64)) {
       // Check if an immediate VMOV works.
       EVT VmovVT;
-      SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
-                                      SplatUndef.getZExtValue(), SplatBitSize,
-                                      DAG, dl, VmovVT, VT.is128BitVector(),
-                                      VMOVModImm);
+      SDValue Val =
+          isVMOVModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
+                            SplatBitSize, DAG, dl, VmovVT, VT, VMOVModImm);
 
       if (Val.getNode()) {
         SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
       }
 
       // Try an immediate VMVN.
       uint64_t NegatedImm = (~SplatBits).getZExtValue();
       Val = isVMOVModifiedImm(
-          NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
-          DAG, dl, VmovVT, VT.is128BitVector(),
-          ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);
+          NegatedImm, SplatUndef.getZExtValue(), SplatBitSize, DAG, dl, VmovVT,
+          VT, ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);
       if (Val.getNode()) {
         SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
       }
 
       // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
       if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
         int ImmVal = ARM_AM::getFP32Imm(SplatBits);
static SDValue PerformANDCombine(SDNode *N,
   unsigned SplatBitSize;
   bool HasAnyUndefs;
   if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) &&
       BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
     if (SplatBitSize <= 64) {
       EVT VbicVT;
       SDValue Val = isVMOVModifiedImm((~SplatBits).getZExtValue(),
                                       SplatUndef.getZExtValue(), SplatBitSize,
-                                      DAG, dl, VbicVT, VT.is128BitVector(),
-                                      OtherModImm);
+                                      DAG, dl, VbicVT, VT, OtherModImm);
       if (Val.getNode()) {
         SDValue Input =
           DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
         SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
         return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
       }
     }
   }
static SDValue PerformORCombine(SDNode *N,
 
   APInt SplatBits, SplatUndef;
   unsigned SplatBitSize;
   bool HasAnyUndefs;
   if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) &&
       BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
     if (SplatBitSize <= 64) {
       EVT VorrVT;
-      SDValue Val = isVMOVModifiedImm(SplatBits.getZExtValue(),
-                                      SplatUndef.getZExtValue(), SplatBitSize,
-                                      DAG, dl, VorrVT, VT.is128BitVector(),
-                                      OtherModImm);
+      SDValue Val =
+          isVMOVModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
+                            SplatBitSize, DAG, dl, VorrVT, VT, OtherModImm);
       if (Val.getNode()) {
         SDValue Input =
           DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
         SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
         return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
       }
     }
   }

llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll

entry:
   %z = fadd <4 x half> %v, %w
   store <4 x half> %z, <4 x half>* %store
   ret void
 }
 
 define void @conv_v4i16_to_v4f16( <4 x i16> %a, <4 x half>* %store ) {
 ; CHECK-LABEL: conv_v4i16_to_v4f16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i64 d16, #0xffffffff0000
+; CHECK-NEXT:    vmov.i64 d16, #0xffff00000000ffff
 ; CHECK-NEXT:    vldr d17, [r0]
 ; CHECK-NEXT:    vrev64.16 d18, d0
 ; CHECK-NEXT:    vrev64.16 d17, d17
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vadd.i16 d16, d18, d16
 ; CHECK-NEXT:    vadd.f16 d16, d16, d17
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]

llvm/test/CodeGen/ARM/big-endian-vmov.ll

+; RUN: llc < %s -mtriple armv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+; RUN: llc < %s -mtriple armebv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+
+; CHECK-LABEL: vmov_i8
+; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <8 x i8> @vmov_i8() {
+  ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1>
+}
+
+; CHECK-LABEL: vmov_i16_a:
+; CHECK-LE: vmov.i64 d0, #0xffff000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xffff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <4 x i16> @vmov_i16_a() {
+  ret <4 x i16> <i16 0, i16 0, i16 0, i16 -1>
+}
+
+; CHECK-LABEL: vmov_i16_b:
+; CHECK-LE: vmov.i64 d0, #0xff000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <4 x i16> @vmov_i16_b() {
+  ret <4 x i16> <i16 0, i16 0, i16 0, i16 255>
+}
+
+; CHECK-LABEL: vmov_i16_c:
+; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff00{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <4 x i16> @vmov_i16_c() {
+  ret <4 x i16> <i16 0, i16 0, i16 0, i16 65280>
+}
+
+; CHECK-LABEL: vmov_i32_a:
+; CHECK-LE: vmov.i64 d0, #0xffffffff00000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xffffffff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <2 x i32> @vmov_i32_a() {
+  ret <2 x i32> <i32 0, i32 -1>
+}
+
+; CHECK-LABEL: vmov_i32_b:
+; CHECK-LE: vmov.i64 d0, #0xff00000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <2 x i32> @vmov_i32_b() {
+  ret <2 x i32> <i32 0, i32 255>
+}
+
+; CHECK-LABEL: vmov_i32_c:
+; CHECK-LE: vmov.i64 d0, #0xff0000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff00{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <2 x i32> @vmov_i32_c() {
+  ret <2 x i32> <i32 0, i32 65280>
+}
+
+; CHECK-LABEL: vmov_i32_d:
+; CHECK-LE: vmov.i64 d0, #0xff000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff0000{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <2 x i32> @vmov_i32_d() {
+  ret <2 x i32> <i32 0, i32 16711680>
+}
+
+; CHECK-LABEL: vmov_i32_e:
+; CHECK-LE: vmov.i64 d0, #0xff00000000000000{{$}}
+; CHECK-BE: vmov.i64 d0, #0xff000000{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <2 x i32> @vmov_i32_e() {
+  ret <2 x i32> <i32 0, i32 4278190080>
+}
+
+; CHECK-LABEL: vmov_i64_a:
+; CHECK: vmov.i8 d0, #0xff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() {
+  ret <1 x i64> <i64 -1>
+}
+
+; CHECK-LABEL: vmov_i64_b:
+; CHECK: vmov.i64 d0, #0xffff00ff0000ff{{$}}
+; CHECK-NEXT: bx lr
+define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
+  ret <1 x i64> <i64 72056498804490495>
+}

llvm/test/CodeGen/ARM/vmov.ll

 ; CHECK-LABEL: v_movQi32f:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov.i32 q0, #0x20ffff
 ; CHECK-NEXT:    mov pc, lr
   ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
 }
 
 define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
-; CHECK-LE-LABEL: v_movQi64:
-; CHECK-LE:       @ %bb.0:
-; CHECK-LE-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
-; CHECK-LE-NEXT:    mov pc, lr
-;
-; CHECK-BE-LABEL: v_movQi64:
-; CHECK-BE:       @ %bb.0:
-; CHECK-BE-NEXT:    vmov.i64 q0, #0xffffff0000ff
-; CHECK-BE-NEXT:    mov pc, lr
+; CHECK-LABEL: v_movQi64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
+; CHECK-NEXT:    mov pc, lr
   ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
 }
 
 ; Check for correct assembler printing for immediate values.
 %struct.int8x8_t = type { <8 x i8> }
 define arm_aapcs_vfpcc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
 ; CHECK-LABEL: vdupn128:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/Thumb2/mve-vmovimm.ll

 ; CHECKBE-NEXT:    .long 1
 ; CHECKBE-NEXT:    .long 0 @ double 4.9406564584124654E-324
 ; CHECKBE-NEXT:    .long 1
 entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() {
-; CHECKLE-LABEL: mov_int64_ff:
-; CHECKLE:       @ %bb.0: @ %entry
-; CHECKLE-NEXT:    vmov.i64 q0, #0xff
-; CHECKLE-NEXT:    bx lr
-;
-; CHECKBE-LABEL: mov_int64_ff:
-; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q0, #0xff00000000
-; CHECKBE-NEXT:    bx lr
+; CHECK-LABEL: mov_int64_ff:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i64 q0, #0xff
+; CHECK-NEXT:    bx lr
 entry:
   ret <2 x i64> < i64 255, i64 255 >
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
 ; CHECK-LABEL: mov_int64_m1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.i8 q0, #0xff
 ; CHECK-NEXT:    bx lr
 entry:
   ret <2 x i64> < i64 -1, i64 -1 >
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {
-; CHECKLE-LABEL: mov_int64_ff0000ff0000ffff:
-; CHECKLE:       @ %bb.0: @ %entry
-; CHECKLE-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
-; CHECKLE-NEXT:    bx lr
-;
-; CHECKBE-LABEL: mov_int64_ff0000ff0000ffff:
-; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q0, #0xffffff0000ff
-; CHECKBE-NEXT:    bx lr
+; CHECK-LABEL: mov_int64_ff0000ff0000ffff:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
+; CHECK-NEXT:    bx lr
 entry:
   ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
 ; CHECKLE-LABEL: mov_int64_f_0:
 ; CHECKLE:       @ %bb.0: @ %entry
 ; CHECKLE-NEXT:    adr r0, .LCPI22_0

 define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() {
 ; CHECKLE-LABEL: mov_int64_0f000f0f:
 ; CHECKLE:       @ %bb.0: @ %entry
 ; CHECKLE-NEXT:    vmov.i64 q0, #0xff000000ff00ff
 ; CHECKLE-NEXT:    bx lr
 ;
 ; CHECKBE-LABEL: mov_int64_0f000f0f:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q0, #0xff00ff00ff00
+; CHECKBE-NEXT:    vmov.i64 q0, #0xff00ff000000ff00
 ; CHECKBE-NEXT:    bx lr
 entry:
   ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
 }
 
 define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() {
 ; CHECKLE-LABEL: mov_int64_ff00ffff:
 ; CHECKLE:       @ %bb.0: @ %entry
 ; CHECKLE-NEXT:    vmov.i64 q0, #0xffffffff0000ffff
 ; CHECKLE-NEXT:    bx lr
 ;
 ; CHECKBE-LABEL: mov_int64_ff00ffff:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q0, #0xffffffffffff0000
+; CHECKBE-NEXT:    vmov.i64 q0, #0xffff0000ffffffff
 ; CHECKBE-NEXT:    bx lr
 entry:
   ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
 }
 
 define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {
 ; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
 ; CHECKLE:       @ %bb.0: @ %entry

 ; CHECKLE-LABEL: test:
 ; CHECKLE:       @ %bb.0: @ %entry
 ; CHECKLE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
 ; CHECKLE-NEXT:    vorr q0, q0, q1
 ; CHECKLE-NEXT:    bx lr
 ;
 ; CHECKBE-LABEL: test:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q1, #0xff00ff00ff0000
+; CHECKBE-NEXT:    vmov.i64 q1, #0xff00ff000000ff00
 ; CHECKBE-NEXT:    vrev64.8 q2, q1
 ; CHECKBE-NEXT:    vrev64.8 q1, q0
 ; CHECKBE-NEXT:    vorr q1, q1, q2
 ; CHECKBE-NEXT:    vrev64.8 q0, q1
 ; CHECKBE-NEXT:    bx lr
 entry:
   %o = or <16 x i8> %i, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
   ret <16 x i8> %o
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {
 ; CHECKLE-LABEL: test2:
 ; CHECKLE:       @ %bb.0: @ %entry
 ; CHECKLE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
 ; CHECKLE-NEXT:    vorr q0, q0, q1
 ; CHECKLE-NEXT:    bx lr
 ;
 ; CHECKBE-LABEL: test2:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    vmov.i64 q1, #0xffffffffffff
+; CHECKBE-NEXT:    vmov.i64 q1, #0xffff0000ffffffff
 ; CHECKBE-NEXT:    vrev64.16 q2, q1
 ; CHECKBE-NEXT:    vrev64.16 q1, q0
 ; CHECKBE-NEXT:    vorr q1, q1, q2
 ; CHECKBE-NEXT:    vrev64.16 q0, q1
 ; CHECKBE-NEXT:    bx lr
 entry:
   %o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
   ret <8 x i16> %o
 }