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Differential D76023

[ARM] Sink splats to vector float instructions
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Authored by dmgreen on Mar 11 2020, 1:33 PM.

Details

Reviewers
SjoerdMeijer
simon_tatham
samparker
ostannard
Commits
rG37b9cc8f29e9: [ARM] Sink splats to vector float instructions
Summary

Some MVE floating point instruction have gpr register variants that take the scalar gpr value and splat them to all lanes. In order to accept them in loops, the shuffle_vector and insert need to be sunk down into the loop, next to the instruction so that ISel can see the whole pattern.

This does that sinking for FAdd, FSub, FMul and FCmp. The patterns for mul are slightly more constrained as there are no fms variants taking register arguments.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 11 2020, 1:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 11 2020, 1:33 PM
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samparker added a comment.Mar 12 2020, 2:41 AM

Annoying about the vmovs.... I can't see, with register aliasing, how this codegen wouldn't be a regression.

llvm/test/CodeGen/Thumb2/mve-floatregloops.ll
644 ↗(On Diff #249738)

So why has this caused the vdup to not be hoisted anymore?

dmgreen marked an inline comment as done.Mar 12 2020, 7:17 AM
In D76023#1918962, @samparker wrote:

Annoying about the vmovs.... I can't see, with register aliasing, how this codegen wouldn't be a regression.

Certainly would be on it's own, but people will be writing similar code with intrinsics anyway so is something we need to get sorted. The second part is in D76024 if you didn't already see it. Plan is to commit them together, but I needed the tests from here to test that patch.

llvm/test/CodeGen/Thumb2/mve-floatregloops.ll
644 ↗(On Diff #249738)

The vdup depends on the vmov and the vmov isn't hoisted.

samparker accepted this revision.Mar 13 2020, 5:03 AM

Ok, if this unblocks the LICM, then LGTM.

llvm/test/CodeGen/Thumb2/mve-floatregloops.ll
644 ↗(On Diff #249738)

facepalm.

This revision is now accepted and ready to land.Mar 13 2020, 5:03 AM
dmgreen updated this revision to Diff 251998.Mar 23 2020, 5:36 AM
dmgreen edited the summary of this revision. (Show Details)

Rebased onto the VDUP type changes.

samparker accepted this revision.Mar 23 2020, 6:41 AM

Nice.

Closed by commit rG37b9cc8f29e9: [ARM] Sink splats to vector float instructions (authored by dmgreen). · Explain WhyMar 26 2020, 2:08 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
14 lines
test/
CodeGen/
Thumb2/
228 lines
234 lines
66 lines

Diff 252774

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 15,506 Lines • ▼ Show 20 Lines if (Subtarget->hasNEON()) {
default: default:
return false; return false;
} }
} }
if (!Subtarget->hasMVEIntegerOps()) if (!Subtarget->hasMVEIntegerOps())
return false; return false;
auto IsSinker = [](Instruction *I, int Operand) { auto IsFMSMul = [&](Instruction *I) {
if (!I->hasOneUse())
return false;
auto *Sub = cast<Instruction>(*I->users().begin());
return Sub->getOpcode() == Instruction::FSub && Sub->getOperand(1) == I;
};
auto IsSinker = [&](Instruction *I, int Operand) {
switch (I->getOpcode()) { switch (I->getOpcode()) {
case Instruction::Add: case Instruction::Add:
case Instruction::Mul: case Instruction::Mul:
case Instruction::FAdd:
case Instruction::ICmp: case Instruction::ICmp:
case Instruction::FCmp:
return true; return true;
case Instruction::FMul:
return !IsFMSMul(I);
case Instruction::Sub: case Instruction::Sub:
case Instruction::FSub:
case Instruction::Shl: case Instruction::Shl:
case Instruction::LShr: case Instruction::LShr:
case Instruction::AShr: case Instruction::AShr:
return Operand == 1; return Operand == 1;
default: default:
return false; return false;
} }
}; };
▲ Show 20 Lines • Show All 2,559 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-float16regloops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc void @test_fadd(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fadd(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd: ; CHECK-LABEL: test_fadd:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vdup.16 q0, r1
; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: .LBB0_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r3, #8 ; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: vadd.f16 q1, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q0, r1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB0_1 ; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%B = load half, half* %BB %B = load half, half* %BB
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 25 Lines
define arm_aapcs_vfpcc void @test_fadd_r(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fadd_r(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd_r: ; CHECK-LABEL: test_fadd_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vdup.16 q0, r1
; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: .LBB1_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r3, #8 ; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: vadd.f16 q1, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, r1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB1_1 ; CHECK-NEXT: bne .LBB1_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%B = load half, half* %BB %B = load half, half* %BB
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 25 Lines
define arm_aapcs_vfpcc void @test_fmul(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fmul(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fmul: ; CHECK-LABEL: test_fmul:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vdup.16 q0, r1
; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: .LBB2_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r3, #8 ; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: vmul.f16 q1, q1, q0 ; CHECK-NEXT: vmul.f16 q0, q0, r1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB2_1 ; CHECK-NEXT: bne .LBB2_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%B = load half, half* %BB %B = load half, half* %BB
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 25 Lines
define arm_aapcs_vfpcc void @test_fmul_r(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fmul_r(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fmul_r: ; CHECK-LABEL: test_fmul_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vdup.16 q0, r1
; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: .LBB3_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r3, #8 ; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: vmul.f16 q1, q0, q1 ; CHECK-NEXT: vmul.f16 q0, q0, r1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB3_1 ; CHECK-NEXT: bne .LBB3_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%B = load half, half* %BB %B = load half, half* %BB
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 25 Lines
define arm_aapcs_vfpcc void @test_fsub(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fsub(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fsub: ; CHECK-LABEL: test_fsub:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vdup.16 q0, r1
; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: .LBB4_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r3, #8 ; CHECK-NEXT: subs r3, #8
; CHECK-NEXT: vsub.f16 q1, q1, q0 ; CHECK-NEXT: vsub.f16 q0, q0, r1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB4_1 ; CHECK-NEXT: bne .LBB4_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%B = load half, half* %BB %B = load half, half* %BB
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
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; CHECK-LABEL: test_fmas: ; CHECK-LABEL: test_fmas:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: .LBB6_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vfma.f16 q3, q2, q1 ; CHECK-NEXT: vfmas.f16 q1, q0, r2
; CHECK-NEXT: vstrb.8 q3, [r3], #16 ; CHECK-NEXT: vstrb.8 q1, [r3], #16
; CHECK-NEXT: bne .LBB6_1 ; CHECK-NEXT: bne .LBB6_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 30 Lines
; CHECK-LABEL: test_fmas_r: ; CHECK-LABEL: test_fmas_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: .LBB7_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vfma.f16 q3, q2, q1 ; CHECK-NEXT: vfmas.f16 q1, q0, r2
; CHECK-NEXT: vstrb.8 q3, [r3], #16 ; CHECK-NEXT: vstrb.8 q1, [r3], #16
; CHECK-NEXT: bne .LBB7_1 ; CHECK-NEXT: bne .LBB7_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 30 Lines
; CHECK-LABEL: test_fma: ; CHECK-LABEL: test_fma:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vfma.f16 q2, q1, q0 ; CHECK-NEXT: vfma.f16 q1, q0, r2
; CHECK-NEXT: vstrb.8 q2, [r3], #16 ; CHECK-NEXT: vstrb.8 q1, [r3], #16
; CHECK-NEXT: bne .LBB8_1 ; CHECK-NEXT: bne .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 30 Lines
; CHECK-LABEL: test_fma_r: ; CHECK-LABEL: test_fma_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: .LBB9_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vfma.f16 q2, q0, q1 ; CHECK-NEXT: vfma.f16 q1, q0, r2
; CHECK-NEXT: vstrb.8 q2, [r3], #16 ; CHECK-NEXT: vstrb.8 q1, [r3], #16
; CHECK-NEXT: bne .LBB9_1 ; CHECK-NEXT: bne .LBB9_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
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; CHECK-LABEL: test_fms: ; CHECK-LABEL: test_fms:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB12_1: @ %vector.body ; CHECK-NEXT: .LBB12_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vneg.f16 q1, q1 ; CHECK-NEXT: vneg.f16 q0, q0
; CHECK-NEXT: vfma.f16 q1, q2, q0 ; CHECK-NEXT: vfma.f16 q0, q1, r2
; CHECK-NEXT: vstrb.8 q1, [r3], #16 ; CHECK-NEXT: vstrb.8 q0, [r3], #16
; CHECK-NEXT: bne .LBB12_1 ; CHECK-NEXT: bne .LBB12_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
Show All 30 Lines
; CHECK-LABEL: test_fms_r: ; CHECK-LABEL: test_fms_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr.w r12, [sp] ; CHECK-NEXT: ldr.w r12, [sp]
; CHECK-NEXT: cmp.w r12, #1 ; CHECK-NEXT: cmp.w r12, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vldr.16 s0, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB13_1: @ %vector.body ; CHECK-NEXT: .LBB13_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: subs.w r12, r12, #8 ; CHECK-NEXT: subs.w r12, r12, #8
; CHECK-NEXT: vneg.f16 q1, q1 ; CHECK-NEXT: vneg.f16 q0, q0
; CHECK-NEXT: vfma.f16 q1, q0, q2 ; CHECK-NEXT: vfma.f16 q0, q1, r2
; CHECK-NEXT: vstrb.8 q1, [r3], #16 ; CHECK-NEXT: vstrb.8 q0, [r3], #16
; CHECK-NEXT: bne .LBB13_1 ; CHECK-NEXT: bne .LBB13_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%C = load half, half* %CC %C = load half, half* %CC
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
for.end14: ; preds = %for.cond6.for.end_crit_edge.us for.end14: ; preds = %for.cond6.for.end_crit_edge.us
ret void ret void
} }
%struct.arm_fir_instance_f32 = type { i16, half*, half* } %struct.arm_fir_instance_f32 = type { i16, half*, half* }
define void @arm_fir_f32_1_4_mve(%struct.arm_fir_instance_f32* nocapture readonly %S, half* nocapture readonly %pSrc, half* %pDst, i32 %blockSize) { define void @arm_fir_f32_1_4_mve(%struct.arm_fir_instance_f32* nocapture readonly %S, half* nocapture readonly %pSrc, half* %pDst, i32 %blockSize) {
; CHECK-LABEL: arm_fir_f32_1_4_mve: ; CHECK-LABEL: arm_fir_f32_1_4_mve:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .pad #16
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: ldrh.w r10, [r0] ; CHECK-NEXT: ldrh r4, [r0]
; CHECK-NEXT: ldr.w r12, [r0, #4] ; CHECK-NEXT: ldr r5, [r0, #4]
; CHECK-NEXT: sub.w r7, r10, #1 ; CHECK-NEXT: subs r7, r4, #1
; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: cmp r7, #3
; CHECK-NEXT: bhi .LBB15_6 ; CHECK-NEXT: bhi .LBB15_6
; CHECK-NEXT: @ %bb.1: @ %if.then ; CHECK-NEXT: @ %bb.1: @ %if.then
; CHECK-NEXT: ldr r6, [r0, #8] ; CHECK-NEXT: ldr r6, [r0, #8]
; CHECK-NEXT: add.w r11, r5, r7, lsl #1
; CHECK-NEXT: lsr.w lr, r3, #2 ; CHECK-NEXT: lsr.w lr, r3, #2
; CHECK-NEXT: ldrh r4, [r6, #6] ; CHECK-NEXT: vldr.16 s0, [r6, #6]
; CHECK-NEXT: vdup.16 q0, r4 ; CHECK-NEXT: vldr.16 s2, [r6, #4]
; CHECK-NEXT: ldrh r4, [r6, #4] ; CHECK-NEXT: vldr.16 s4, [r6, #2]
; CHECK-NEXT: vdup.16 q1, r4 ; CHECK-NEXT: vldr.16 s6, [r6]
; CHECK-NEXT: ldrh r4, [r6, #2]
; CHECK-NEXT: ldrh r6, [r6]
; CHECK-NEXT: vdup.16 q2, r4
; CHECK-NEXT: add.w r4, r12, r7, lsl #1
; CHECK-NEXT: vdup.16 q3, r6
; CHECK-NEXT: wls lr, lr, .LBB15_5 ; CHECK-NEXT: wls lr, lr, .LBB15_5
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
; CHECK-NEXT: bic r9, r3, #3 ; CHECK-NEXT: strd r3, r4, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: vmov.f16 r10, s6
; CHECK-NEXT: vmov.f16 r12, s4
; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: vmov.f16 r4, s2
; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-NEXT: vmov.f16 r8, s0
; CHECK-NEXT: add.w r3, r2, r3, lsl #1
; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: movs r6, #0 ; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: add.w r8, r2, r9, lsl #1 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: .LBB15_3: @ %while.body ; CHECK-NEXT: .LBB15_3: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: adds r7, r1, r6 ; CHECK-NEXT: add.w r9, r1, r6
; CHECK-NEXT: vldrw.u32 q4, [r7] ; CHECK-NEXT: add.w r7, r11, r6
; CHECK-NEXT: adds r7, r4, r6 ; CHECK-NEXT: vldrw.u32 q2, [r9]
; CHECK-NEXT: vstrw.32 q4, [r7] ; CHECK-NEXT: vstrw.32 q2, [r7]
; CHECK-NEXT: add.w r7, r12, r6 ; CHECK-NEXT: adds r7, r3, r6
; CHECK-NEXT: vldrw.u32 q4, [r7] ; CHECK-NEXT: vldrw.u32 q2, [r7]
; CHECK-NEXT: adds r5, r7, #2 ; CHECK-NEXT: adds r5, r7, #2
; CHECK-NEXT: vldrw.u32 q5, [r5] ; CHECK-NEXT: vldrw.u32 q3, [r5]
; CHECK-NEXT: adds r5, r7, #6 ; CHECK-NEXT: adds r5, r7, #6
; CHECK-NEXT: vmul.f16 q4, q4, q3 ; CHECK-NEXT: vmul.f16 q2, q2, r10
; CHECK-NEXT: vfma.f16 q4, q5, q2 ; CHECK-NEXT: vfma.f16 q2, q3, r12
; CHECK-NEXT: vldrw.u32 q5, [r7, #4] ; CHECK-NEXT: vldrw.u32 q3, [r7, #4]
; CHECK-NEXT: vfma.f16 q4, q5, q1 ; CHECK-NEXT: vfma.f16 q2, q3, r4
; CHECK-NEXT: vldrw.u32 q5, [r5] ; CHECK-NEXT: vldrw.u32 q3, [r5]
; CHECK-NEXT: adds r5, r2, r6 ; CHECK-NEXT: adds r5, r2, r6
; CHECK-NEXT: adds r6, #8 ; CHECK-NEXT: adds r6, #8
; CHECK-NEXT: vfma.f16 q4, q5, q0 ; CHECK-NEXT: vfma.f16 q2, q3, r8
; CHECK-NEXT: vstrw.32 q4, [r5] ; CHECK-NEXT: vstrw.32 q2, [r5]
; CHECK-NEXT: le lr, .LBB15_3 ; CHECK-NEXT: le lr, .LBB15_3
; CHECK-NEXT: @ %bb.4: @ %while.end.loopexit ; CHECK-NEXT: @ %bb.4: @ %while.end.loopexit
; CHECK-NEXT: add r4, r6 ; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-NEXT: add.w r12, r12, r9, lsl #1 ; CHECK-NEXT: add r4, sp, #4
; CHECK-NEXT: add.w r1, r1, r9, lsl #1 ; CHECK-NEXT: add r11, r6
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: add.w r5, r3, r2, lsl #1
; CHECK-NEXT: add.w r1, r1, r2, lsl #1
; CHECK-NEXT: ldm r4, {r2, r3, r4} @ 12-byte Folded Reload
; CHECK-NEXT: .LBB15_5: @ %while.end ; CHECK-NEXT: .LBB15_5: @ %while.end
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r7, r3, #3
; CHECK-NEXT: vldrw.u32 q4, [r1] ; CHECK-NEXT: vldrw.u32 q2, [r1]
; CHECK-NEXT: vctp.16 r7 ; CHECK-NEXT: vctp.16 r7
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q4, [r4] ; CHECK-NEXT: vstrht.16 q2, [r11]
; CHECK-NEXT: vldrw.u32 q4, [r12] ; CHECK-NEXT: vldrw.u32 q2, [r5]
; CHECK-NEXT: add.w r1, r12, #2 ; CHECK-NEXT: vmov.f16 r1, s6
; CHECK-NEXT: vmul.f16 q3, q4, q3 ; CHECK-NEXT: adds r7, r5, #2
; CHECK-NEXT: vldrw.u32 q4, [r1] ; CHECK-NEXT: vmul.f16 q2, q2, r1
; CHECK-NEXT: add.w r1, r12, #6 ; CHECK-NEXT: vmov.f16 r1, s4
; CHECK-NEXT: vfma.f16 q3, q4, q2 ; CHECK-NEXT: vldrw.u32 q1, [r7]
; CHECK-NEXT: vldrw.u32 q2, [r12, #4] ; CHECK-NEXT: adds r7, r5, #6
; CHECK-NEXT: vfma.f16 q3, q2, q1 ; CHECK-NEXT: vfma.f16 q2, q1, r1
; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
; CHECK-NEXT: vfma.f16 q3, q1, q0 ; CHECK-NEXT: vmov.f16 r1, s2
; CHECK-NEXT: vfma.f16 q2, q1, r1
; CHECK-NEXT: vmov.f16 r1, s0
; CHECK-NEXT: vldrw.u32 q0, [r7]
; CHECK-NEXT: vfma.f16 q2, q0, r1
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q3, [r2] ; CHECK-NEXT: vstrht.16 q2, [r2]
; CHECK-NEXT: ldr.w r12, [r0, #4] ; CHECK-NEXT: ldr r5, [r0, #4]
; CHECK-NEXT: .LBB15_6: @ %if.end ; CHECK-NEXT: .LBB15_6: @ %if.end
; CHECK-NEXT: add.w r0, r12, r3, lsl #1 ; CHECK-NEXT: add.w r0, r5, r3, lsl #1
; CHECK-NEXT: lsr.w lr, r10, #2 ; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: lsr.w lr, r4, #2
; CHECK-NEXT: wls lr, lr, .LBB15_10 ; CHECK-NEXT: wls lr, lr, .LBB15_10
; CHECK-NEXT: @ %bb.7: @ %while.body51.preheader ; CHECK-NEXT: @ %bb.7: @ %while.body51.preheader
; CHECK-NEXT: bic r2, r10, #3 ; CHECK-NEXT: bic r7, r4, #3
; CHECK-NEXT: adds r1, r2, r3 ; CHECK-NEXT: adds r1, r7, r3
; CHECK-NEXT: mov r3, r12 ; CHECK-NEXT: mov r3, r2
; CHECK-NEXT: add.w r1, r12, r1, lsl #1 ; CHECK-NEXT: add.w r1, r2, r1, lsl #1
; CHECK-NEXT: .LBB15_8: @ %while.body51 ; CHECK-NEXT: .LBB15_8: @ %while.body51
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r0], #8 ; CHECK-NEXT: vldrw.u32 q0, [r0], #8
; CHECK-NEXT: vstrb.8 q0, [r3], #8 ; CHECK-NEXT: vstrb.8 q0, [r3], #8
; CHECK-NEXT: le lr, .LBB15_8 ; CHECK-NEXT: le lr, .LBB15_8
; CHECK-NEXT: @ %bb.9: @ %while.end55.loopexit ; CHECK-NEXT: @ %bb.9: @ %while.end55.loopexit
; CHECK-NEXT: add.w r12, r12, r2, lsl #1 ; CHECK-NEXT: add.w r2, r2, r7, lsl #1
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: .LBB15_10: @ %while.end55 ; CHECK-NEXT: .LBB15_10: @ %while.end55
; CHECK-NEXT: ands r1, r10, #3 ; CHECK-NEXT: ands r1, r4, #3
; CHECK-NEXT: beq .LBB15_12 ; CHECK-NEXT: beq .LBB15_12
; CHECK-NEXT: @ %bb.11: @ %if.then59 ; CHECK-NEXT: @ %bb.11: @ %if.then59
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vctp.16 r1 ; CHECK-NEXT: vctp.16 r1
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q0, [r12] ; CHECK-NEXT: vstrht.16 q0, [r2]
; CHECK-NEXT: .LBB15_12: @ %if.end61 ; CHECK-NEXT: .LBB15_12: @ %if.end61
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 1 %pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 1
%0 = load half*, half** %pState1, align 4 %0 = load half*, half** %pState1, align 4
%pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 2 %pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 2
%1 = load half*, half** %pCoeffs2, align 4 %1 = load half*, half** %pCoeffs2, align 4
%numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 0 %numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 0
%2 = load i16, i16* %numTaps3, align 4 %2 = load i16, i16* %numTaps3, align 4
%conv = zext i16 %2 to i32 %conv = zext i16 %2 to i32
▲ Show 20 Lines • Show All 541 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-float32regloops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc void @test_fadd(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fadd(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd: ; CHECK-LABEL: test_fadd:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: .LBB0_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vadd.f32 q1, q1, q0 ; CHECK-NEXT: vadd.f32 q0, q0, r3
; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: bne .LBB0_1 ; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp18 = icmp sgt i32 %n, 0 %cmp18 = icmp sgt i32 %n, 0
Show All 23 Lines
define arm_aapcs_vfpcc void @test_fadd_r(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fadd_r(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fadd_r: ; CHECK-LABEL: test_fadd_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: .LBB1_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vadd.f32 q1, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, r3
; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: bne .LBB1_1 ; CHECK-NEXT: bne .LBB1_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp18 = icmp sgt i32 %n, 0 %cmp18 = icmp sgt i32 %n, 0
Show All 23 Lines
define arm_aapcs_vfpcc void @test_fmul(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fmul(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fmul: ; CHECK-LABEL: test_fmul:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: .LBB2_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.f32 q1, q1, q0 ; CHECK-NEXT: vmul.f32 q0, q0, r3
; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: bne .LBB2_1 ; CHECK-NEXT: bne .LBB2_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp18 = icmp sgt i32 %n, 0 %cmp18 = icmp sgt i32 %n, 0
Show All 23 Lines
define arm_aapcs_vfpcc void @test_fmul_r(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fmul_r(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fmul_r: ; CHECK-LABEL: test_fmul_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: .LBB3_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.f32 q1, q0, q1 ; CHECK-NEXT: vmul.f32 q0, q0, r3
; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: bne .LBB3_1 ; CHECK-NEXT: bne .LBB3_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp18 = icmp sgt i32 %n, 0 %cmp18 = icmp sgt i32 %n, 0
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define arm_aapcs_vfpcc void @test_fsub(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { define arm_aapcs_vfpcc void @test_fsub(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) {
; CHECK-LABEL: test_fsub: ; CHECK-LABEL: test_fsub:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: .LBB4_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vsub.f32 q1, q1, q0 ; CHECK-NEXT: vsub.f32 q0, q0, r3
; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: bne .LBB4_1 ; CHECK-NEXT: bne .LBB4_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp18 = icmp sgt i32 %n, 0 %cmp18 = icmp sgt i32 %n, 0
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define arm_aapcs_vfpcc void @test_fmas(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fmas(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fmas: ; CHECK-LABEL: test_fmas:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: .LBB6_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vfma.f32 q3, q2, q1 ; CHECK-NEXT: vfmas.f32 q1, q0, r12
; CHECK-NEXT: vstrb.8 q3, [r2], #16 ; CHECK-NEXT: vstrb.8 q1, [r2], #16
; CHECK-NEXT: bne .LBB6_1 ; CHECK-NEXT: bne .LBB6_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
Show All 27 Lines
define arm_aapcs_vfpcc void @test_fmas_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fmas_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fmas_r: ; CHECK-LABEL: test_fmas_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: .LBB7_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vfma.f32 q3, q2, q1 ; CHECK-NEXT: vfmas.f32 q1, q0, r12
; CHECK-NEXT: vstrb.8 q3, [r2], #16 ; CHECK-NEXT: vstrb.8 q1, [r2], #16
; CHECK-NEXT: bne .LBB7_1 ; CHECK-NEXT: bne .LBB7_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
Show All 27 Lines
define arm_aapcs_vfpcc void @test_fma(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fma(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fma: ; CHECK-LABEL: test_fma:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vfma.f32 q2, q1, q0 ; CHECK-NEXT: vfma.f32 q1, q0, r12
; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: vstrb.8 q1, [r2], #16
; CHECK-NEXT: bne .LBB8_1 ; CHECK-NEXT: bne .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
Show All 27 Lines
define arm_aapcs_vfpcc void @test_fma_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fma_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fma_r: ; CHECK-LABEL: test_fma_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: .LBB9_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vfma.f32 q2, q0, q1 ; CHECK-NEXT: vfma.f32 q1, q0, r12
; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: vstrb.8 q1, [r2], #16
; CHECK-NEXT: bne .LBB9_1 ; CHECK-NEXT: bne .LBB9_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
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define arm_aapcs_vfpcc void @test_fms(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fms(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fms: ; CHECK-LABEL: test_fms:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB12_1: @ %vector.body ; CHECK-NEXT: .LBB12_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vneg.f32 q1, q1 ; CHECK-NEXT: vneg.f32 q0, q0
; CHECK-NEXT: vfma.f32 q1, q2, q0 ; CHECK-NEXT: vfma.f32 q0, q1, r12
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB12_1 ; CHECK-NEXT: bne .LBB12_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
Show All 27 Lines
define arm_aapcs_vfpcc void @test_fms_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) { define arm_aapcs_vfpcc void @test_fms_r(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float %C, float* noalias nocapture %D, i32 %n) {
; CHECK-LABEL: test_fms_r: ; CHECK-LABEL: test_fms_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: cmp r3, #1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: bxlt lr ; CHECK-NEXT: bxlt lr
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: .LBB13_1: @ %vector.body ; CHECK-NEXT: .LBB13_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: vneg.f32 q1, q1 ; CHECK-NEXT: vneg.f32 q0, q0
; CHECK-NEXT: vfma.f32 q1, q0, q2 ; CHECK-NEXT: vfma.f32 q0, q1, r12
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: bne .LBB13_1 ; CHECK-NEXT: bne .LBB13_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and i32 %n, 7 %0 = and i32 %n, 7
%cmp = icmp eq i32 %0, 0 %cmp = icmp eq i32 %0, 0
tail call void @llvm.assume(i1 %cmp) tail call void @llvm.assume(i1 %cmp)
%cmp110 = icmp sgt i32 %n, 0 %cmp110 = icmp sgt i32 %n, 0
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
for.end14: ; preds = %for.cond6.for.end_crit_edge.us for.end14: ; preds = %for.cond6.for.end_crit_edge.us
ret void ret void
} }
%struct.arm_fir_instance_f32 = type { i16, float*, float* } %struct.arm_fir_instance_f32 = type { i16, float*, float* }
define void @arm_fir_f32_1_4_mve(%struct.arm_fir_instance_f32* nocapture readonly %S, float* nocapture readonly %pSrc, float* %pDst, i32 %blockSize) { define void @arm_fir_f32_1_4_mve(%struct.arm_fir_instance_f32* nocapture readonly %S, float* nocapture readonly %pSrc, float* %pDst, i32 %blockSize) {
; CHECK-LABEL: arm_fir_f32_1_4_mve: ; CHECK-LABEL: arm_fir_f32_1_4_mve:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .pad #4
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: ldrh.w r9, [r0] ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: ldr.w r12, [r0, #4] ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: sub.w r7, r9, #1 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: ldrh r4, [r0]
; CHECK-NEXT: ldr.w r11, [r0, #4]
; CHECK-NEXT: subs r7, r4, #1
; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: cmp r7, #3
; CHECK-NEXT: bhi .LBB15_6 ; CHECK-NEXT: bhi .LBB15_6
; CHECK-NEXT: @ %bb.1: @ %if.then ; CHECK-NEXT: @ %bb.1: @ %if.then
; CHECK-NEXT: ldr r6, [r0, #8] ; CHECK-NEXT: ldr r6, [r0, #8]
; CHECK-NEXT: add.w r4, r12, r7, lsl #2 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: ldrd lr, r8, [r6] ; CHECK-NEXT: add.w r0, r11, r7, lsl #2
; CHECK-NEXT: ldrd r5, r6, [r6, #8]
; CHECK-NEXT: vdup.32 q3, lr
; CHECK-NEXT: vdup.32 q2, r8
; CHECK-NEXT: vdup.32 q0, r6
; CHECK-NEXT: vdup.32 q1, r5
; CHECK-NEXT: lsr.w lr, r3, #2 ; CHECK-NEXT: lsr.w lr, r3, #2
; CHECK-NEXT: vldr s0, [r6]
; CHECK-NEXT: vldr s2, [r6, #4]
; CHECK-NEXT: vldr s4, [r6, #8]
; CHECK-NEXT: vldr s6, [r6, #12]
; CHECK-NEXT: wls lr, lr, .LBB15_5 ; CHECK-NEXT: wls lr, lr, .LBB15_5
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
; CHECK-NEXT: bic r10, r3, #3 ; CHECK-NEXT: strd r5, r3, [sp, #12] @ 8-byte Folded Spill
; CHECK-NEXT: vmov r7, s4
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: vmov r5, s6
; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: vmov r8, s0
; CHECK-NEXT: movs r6, #0 ; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: add.w r8, r2, r10, lsl #2 ; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: add.w r3, r2, r3, lsl #2
; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: .LBB15_3: @ %while.body ; CHECK-NEXT: .LBB15_3: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: adds r7, r1, r6 ; CHECK-NEXT: add.w r10, r1, r6
; CHECK-NEXT: adds r5, r2, r6 ; CHECK-NEXT: adds r3, r0, r6
; CHECK-NEXT: vldrw.u32 q4, [r7] ; CHECK-NEXT: vldrw.u32 q2, [r10]
; CHECK-NEXT: adds r7, r4, r6 ; CHECK-NEXT: add.w r12, r11, r6
; CHECK-NEXT: vstrw.32 q4, [r7] ; CHECK-NEXT: add.w r9, r2, r6
; CHECK-NEXT: add.w r7, r12, r6
; CHECK-NEXT: vldrw.u32 q4, [r7]
; CHECK-NEXT: vldrw.u32 q5, [r7, #4]
; CHECK-NEXT: vldrw.u32 q6, [r7, #12]
; CHECK-NEXT: adds r6, #16 ; CHECK-NEXT: adds r6, #16
; CHECK-NEXT: vmul.f32 q4, q4, q3 ; CHECK-NEXT: vstrw.32 q2, [r3]
; CHECK-NEXT: vfma.f32 q4, q5, q2 ; CHECK-NEXT: vldrw.u32 q2, [r12]
; CHECK-NEXT: vldrw.u32 q5, [r7, #8] ; CHECK-NEXT: vldrw.u32 q3, [r12, #4]
; CHECK-NEXT: vfma.f32 q4, q5, q1 ; CHECK-NEXT: vldrw.u32 q4, [r12, #12]
; CHECK-NEXT: vfma.f32 q4, q6, q0 ; CHECK-NEXT: vmul.f32 q2, q2, r8
; CHECK-NEXT: vstrw.32 q4, [r5] ; CHECK-NEXT: vfma.f32 q2, q3, r4
; CHECK-NEXT: vldrw.u32 q3, [r12, #8]
; CHECK-NEXT: vfma.f32 q2, q3, r7
; CHECK-NEXT: vfma.f32 q2, q4, r5
; CHECK-NEXT: vstrw.32 q2, [r9]
; CHECK-NEXT: le lr, .LBB15_3 ; CHECK-NEXT: le lr, .LBB15_3
; CHECK-NEXT: @ %bb.4: @ %while.end.loopexit ; CHECK-NEXT: @ %bb.4: @ %while.end.loopexit
; CHECK-NEXT: add r4, r6 ; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: add.w r12, r12, r10, lsl #2 ; CHECK-NEXT: add r0, r6
; CHECK-NEXT: add.w r1, r1, r10, lsl #2 ; CHECK-NEXT: ldrd r3, r4, [sp, #16] @ 8-byte Folded Reload
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: add.w r11, r11, r2, lsl #2
; CHECK-NEXT: add.w r1, r1, r2, lsl #2
; CHECK-NEXT: ldrd r2, r5, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: .LBB15_5: @ %while.end ; CHECK-NEXT: .LBB15_5: @ %while.end
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r6, r3, #3
; CHECK-NEXT: vldrw.u32 q4, [r1] ; CHECK-NEXT: vmov r12, s6
; CHECK-NEXT: vctp.32 r7 ; CHECK-NEXT: vmov lr, s4
; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vctp.32 r6
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrwt.32 q4, [r4] ; CHECK-NEXT: vstrwt.32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r12] ; CHECK-NEXT: vmov r9, s2
; CHECK-NEXT: vmul.f32 q3, q4, q3 ; CHECK-NEXT: vldrw.u32 q1, [r11, #4]
; CHECK-NEXT: vldrw.u32 q4, [r12, #4] ; CHECK-NEXT: vmov r7, s0
; CHECK-NEXT: vfma.f32 q3, q4, q2 ; CHECK-NEXT: vldrw.u32 q0, [r11]
; CHECK-NEXT: vldrw.u32 q2, [r12, #8] ; CHECK-NEXT: vmul.f32 q0, q0, r7
; CHECK-NEXT: vfma.f32 q3, q2, q1 ; CHECK-NEXT: vfma.f32 q0, q1, r9
; CHECK-NEXT: vldrw.u32 q1, [r12, #12] ; CHECK-NEXT: vldrw.u32 q1, [r11, #8]
; CHECK-NEXT: vfma.f32 q3, q1, q0 ; CHECK-NEXT: vfma.f32 q0, q1, lr
; CHECK-NEXT: vldrw.u32 q1, [r11, #12]
; CHECK-NEXT: vfma.f32 q0, q1, r12
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrwt.32 q3, [r2] ; CHECK-NEXT: vstrwt.32 q0, [r2]
; CHECK-NEXT: ldr.w r12, [r0, #4] ; CHECK-NEXT: ldr.w r11, [r5, #4]
; CHECK-NEXT: .LBB15_6: @ %if.end ; CHECK-NEXT: .LBB15_6: @ %if.end
; CHECK-NEXT: add.w r0, r12, r3, lsl #2 ; CHECK-NEXT: add.w r0, r11, r3, lsl #2
; CHECK-NEXT: lsr.w lr, r9, #2 ; CHECK-NEXT: lsr.w lr, r4, #2
; CHECK-NEXT: wls lr, lr, .LBB15_10 ; CHECK-NEXT: wls lr, lr, .LBB15_10
; CHECK-NEXT: @ %bb.7: @ %while.body51.preheader ; CHECK-NEXT: @ %bb.7: @ %while.body51.preheader
; CHECK-NEXT: bic r2, r9, #3 ; CHECK-NEXT: bic r7, r4, #3
; CHECK-NEXT: adds r1, r2, r3 ; CHECK-NEXT: adds r1, r7, r3
; CHECK-NEXT: mov r3, r12 ; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: add.w r1, r12, r1, lsl #2 ; CHECK-NEXT: add.w r1, r11, r1, lsl #2
; CHECK-NEXT: .LBB15_8: @ %while.body51 ; CHECK-NEXT: .LBB15_8: @ %while.body51
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vstrb.8 q0, [r3], #16 ; CHECK-NEXT: vstrb.8 q0, [r3], #16
; CHECK-NEXT: le lr, .LBB15_8 ; CHECK-NEXT: le lr, .LBB15_8
; CHECK-NEXT: @ %bb.9: @ %while.end55.loopexit ; CHECK-NEXT: @ %bb.9: @ %while.end55.loopexit
; CHECK-NEXT: add.w r12, r12, r2, lsl #2 ; CHECK-NEXT: add.w r11, r11, r7, lsl #2
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: .LBB15_10: @ %while.end55 ; CHECK-NEXT: .LBB15_10: @ %while.end55
; CHECK-NEXT: ands r1, r9, #3 ; CHECK-NEXT: ands r1, r4, #3
; CHECK-NEXT: beq .LBB15_12 ; CHECK-NEXT: beq .LBB15_12
; CHECK-NEXT: @ %bb.11: @ %if.then59 ; CHECK-NEXT: @ %bb.11: @ %if.then59
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vctp.32 r1 ; CHECK-NEXT: vctp.32 r1
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrwt.32 q0, [r12] ; CHECK-NEXT: vstrwt.32 q0, [r11]
; CHECK-NEXT: .LBB15_12: @ %if.end61 ; CHECK-NEXT: .LBB15_12: @ %if.end61
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 1 %pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 1
%0 = load float*, float** %pState1, align 4 %0 = load float*, float** %pState1, align 4
%pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 2 %pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 2
%1 = load float*, float** %pCoeffs2, align 4 %1 = load float*, float** %pCoeffs2, align 4
%numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 0 %numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 0
%2 = load i16, i16* %numTaps3, align 4 %2 = load i16, i16* %numTaps3, align 4
%conv = zext i16 %2 to i32 %conv = zext i16 %2 to i32
▲ Show 20 Lines • Show All 532 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @thresh_f32(float* %data, i16 zeroext %N, float %T) { define arm_aapcs_vfpcc void @thresh_f32(float* %data, i16 zeroext %N, float %T) {
; CHECK-LABEL: thresh_f32: ; CHECK-LABEL: thresh_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: vneg.f32 s2, s0
; CHECK-NEXT: mvn r2, #3 ; CHECK-NEXT: mvn r2, #3
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: add.w lr, r2, r1, lsr #2 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vdup.32 q0, r1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: eor r1, r1, #-2147483648 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vdup.32 q1, r1 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: .LBB3_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpt.f32 le, q0, q3 ; CHECK-NEXT: vpt.f32 ge, q1, r2
; CHECK-NEXT: vcmpt.f32 le, q3, q1 ; CHECK-NEXT: vcmpt.f32 le, q1, r1
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrwt.32 q2, [r0], #16 ; CHECK-NEXT: vstrwt.32 q0, [r0], #16
; CHECK-NEXT: le lr, .LBB3_1 ; CHECK-NEXT: le lr, .LBB3_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%conv = zext i16 %N to i32 %conv = zext i16 %N to i32
%mul = shl nuw nsw i32 %conv, 2 %mul = shl nuw nsw i32 %conv, 2
%cmp15 = icmp eq i16 %N, 0 %cmp15 = icmp eq i16 %N, 0
br i1 %cmp15, label %for.cond.cleanup, label %vector.ph br i1 %cmp15, label %for.cond.cleanup, label %vector.ph
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; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: mvn r2, #7 ; CHECK-NEXT: mvn r2, #7
; CHECK-NEXT: add.w r1, r2, r1, lsl #3 ; CHECK-NEXT: add.w r1, r2, r1, lsl #3
; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: add.w lr, r2, r1, lsr #3 ; CHECK-NEXT: add.w lr, r2, r1, lsr #3
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s2
; CHECK-NEXT: vneg.f16 s0, s0
; CHECK-NEXT: vdup.16 q1, r1
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: .LBB4_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q3, [r0] ; CHECK-NEXT: vldrh.u16 q1, [r0]
; CHECK-NEXT: vpt.f16 le, q1, q3 ; CHECK-NEXT: vpt.f16 ge, q1, r2
; CHECK-NEXT: vcmpt.f16 le, q3, q0 ; CHECK-NEXT: vcmpt.f16 le, q1, r1
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q2, [r0], #16 ; CHECK-NEXT: vstrht.16 q0, [r0], #16
; CHECK-NEXT: le lr, .LBB4_1 ; CHECK-NEXT: le lr, .LBB4_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = bitcast float %T.coerce to i32 %0 = bitcast float %T.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16 %tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half %1 = bitcast i16 %tmp.0.extract.trunc to half
%conv = zext i16 %N to i32 %conv = zext i16 %N to i32
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @thresh_rev_f32(float* %data, i16 zeroext %N, float %T) { define arm_aapcs_vfpcc void @thresh_rev_f32(float* %data, i16 zeroext %N, float %T) {
; CHECK-LABEL: thresh_rev_f32: ; CHECK-LABEL: thresh_rev_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: vneg.f32 s2, s0
; CHECK-NEXT: mvn r2, #3 ; CHECK-NEXT: mvn r2, #3
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: add.w lr, r2, r1, lsr #2 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vdup.32 q0, r1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: eor r1, r1, #-2147483648 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vdup.32 q1, r1 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpt.f32 le, q0, q3 ; CHECK-NEXT: vpt.f32 ge, q1, r2
; CHECK-NEXT: vcmpt.f32 le, q3, q1 ; CHECK-NEXT: vcmpt.f32 le, q1, r1
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrwt.32 q2, [r0], #16 ; CHECK-NEXT: vstrwt.32 q0, [r0], #16
; CHECK-NEXT: le lr, .LBB8_1 ; CHECK-NEXT: le lr, .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%conv = zext i16 %N to i32 %conv = zext i16 %N to i32
%mul = shl nuw nsw i32 %conv, 2 %mul = shl nuw nsw i32 %conv, 2
%cmp15 = icmp eq i16 %N, 0 %cmp15 = icmp eq i16 %N, 0
br i1 %cmp15, label %for.cond.cleanup, label %vector.ph br i1 %cmp15, label %for.cond.cleanup, label %vector.ph
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; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: mvn r2, #7 ; CHECK-NEXT: mvn r2, #7
; CHECK-NEXT: add.w r1, r2, r1, lsl #3 ; CHECK-NEXT: add.w r1, r2, r1, lsl #3
; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: add.w lr, r2, r1, lsr #3 ; CHECK-NEXT: add.w lr, r2, r1, lsr #3
; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vmov.f16 r1, s2
; CHECK-NEXT: vneg.f16 s0, s0
; CHECK-NEXT: vdup.16 q1, r1
; CHECK-NEXT: vmov.f16 r2, s0 ; CHECK-NEXT: vmov.f16 r2, s0
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: vdup.16 q0, r2
; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: .LBB9_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q3, [r0] ; CHECK-NEXT: vldrh.u16 q1, [r0]
; CHECK-NEXT: vpt.f16 le, q1, q3 ; CHECK-NEXT: vpt.f16 ge, q1, r2
; CHECK-NEXT: vcmpt.f16 le, q3, q0 ; CHECK-NEXT: vcmpt.f16 le, q1, r1
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q2, [r0], #16 ; CHECK-NEXT: vstrht.16 q0, [r0], #16
; CHECK-NEXT: le lr, .LBB9_1 ; CHECK-NEXT: le lr, .LBB9_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = bitcast float %T.coerce to i32 %0 = bitcast float %T.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16 %tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half %1 = bitcast i16 %tmp.0.extract.trunc to half
%conv = zext i16 %N to i32 %conv = zext i16 %N to i32
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