[MIPS] Implement PUL.PS and PUU.PS instructions

[atanasyan]

The following test cases failed on my machine. Initially, assembler shows error: unknown instruction. Now assembler shows correct error message instruction requires a CPU feature not currently enabled and the checks should be updated and moved to invalid-xxx.s files.

MC/Mips/mips1/invalid-mips5-wrong-error.s
MC/Mips/mips2/invalid-mips5-wrong-error.s
MC/Mips/mips3/invalid-mips5-wrong-error.s
MC/Mips/mips4/invalid-mips5-wrong-error.s
MC/Mips/mips64r6/invalid-mips5-wrong-error.s

[michael-roe]

This revised patch fixes all the tests that were affected (changed tests from XFAIL to expected pass).

[atanasyan]

LGTM Thanks for the patch.

Do you have commit access?

[michael-roe]

In D75812#1922511, @atanasyan wrote:

LGTM Thanks for the patch.

Do you have commit access?

Thanks!

I don't have commit access; please could someone commit it for me?

llvm/lib/Target/Mips/MipsInstrFPU.td

     def PLU_PS64    : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
                       ADDS_FM<0x2D, 22>,
                       ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def PUL_PS64    : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,
+                      ADDS_FM<0x2E, 22>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def PUU_PS64    : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
+                      ADDS_FM<0x2F, 22>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
 
     def CVT_S_PU64  : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
                       ABSS_FM<0x20, 22>,

llvm/lib/Target/Mips/MipsScheduleGeneric.td

                                   FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
                                   MADD_D32, MADD_D64, MSUB_D32, MSUB_D64,
                                   NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
-                                  PLL_PS64, PLU_PS64,
+                                  PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,
                                   ROUND_L_D64, ROUND_L_S, ROUND_W_D32,
                                   ROUND_W_D64, ROUND_W_S, TRUNC_L_D64,
                                   TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64,

llvm/lib/Target/Mips/MipsScheduleP5600.td

 def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>;
 def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;
 def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>;
-def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>;
+def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>;
 
 // div.[ds], div.ps
 def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;

llvm/test/MC/Mips/mips64r2/valid-xfail.s

         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)

llvm/test/MC/Mips/mips64r2/valid.s

         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
+
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push

llvm/test/MC/Mips/mips64r3/valid-xfail.s

         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)

llvm/test/MC/Mips/mips64r3/valid.s

         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push

llvm/test/MC/Mips/mips64r5/valid-xfail.s

         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)

llvm/test/MC/Mips/mips64r5/valid.s

         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push