AMDGPU: Fix SMRD test in trivially disjoint mem access code

[dstuttard]

Summary

This seems like an obvious error - cut and paste issue?
The change does make a change to one of the lit tests - it stops s_buffer_load
re-ordering past an MUBUF instruction (which is not surprising).

Does it make sense to implement the check for different address spaces as
mentioned in the TODO - that would undo the required change in the test (and
enable more code movement). Is it valid to assume different address spaces can't
alias?

Change-Id: I80be99de5b62af4f42e91af2591b76a52ac9efa6

[arsenm]

This code should not be checking the address space. That will still fall back on the alias analysis pass on the IR in the MMO when available

[foad]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

2676

Not strictly related to your change, but I wonder why this line doesn't return !isSMRD(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb).

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (isMUBUF(MIa) || isMTBUF(MIa)) {
 
     return !isFLAT(MIb) && !isSMRD(MIb);
   }
 
   if (isSMRD(MIa)) {
     if (isSMRD(MIb))
       return checkInstOffsetsDoNotOverlap(MIa, MIb);
 
-    return !isFLAT(MIb) && !isMUBUF(MIa) && !isMTBUF(MIa);
+    return !isFLAT(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb);
   }
 
   if (isFLAT(MIa)) {
     if (isFLAT(MIb))
       return checkInstOffsetsDoNotOverlap(MIa, MIb);
 
     return false;
   }
 
   return false;
 }
 
 static int64_t getFoldableImm(const MachineOperand* MO) {
   if (!MO->isReg())
     return false;

llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

define amdgpu_kernel void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
 
   store i32 %add, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load:
 ; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
-; CI: buffer_store_dword
 
-; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
-; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
+; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
+; CI: buffer_store_dword
+; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
 
 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
 ; GFX9: global_store_dword
 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
 
 ; CI: buffer_store_dword
 ; GFX9: global_store_dword
 define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {