[X86] Fix bug: Scalar FMA intrinsics generate wrong result

[LiuChen3]

Summary

For example, _mm_maskz_fmadd_sd would generate the following assembly:

vmovapd 48(%rsp), %xmm1
vmovapd 32(%rsp), %xmm2
vmovapd 16(%rsp), %xmm0
kmovw %eax, %k1
vfmadd231sd %xmm2, %xmm1, %xmm0 {%k1} {z} # xmm0 = (xmm1 * xmm2) + xmm0

In some cases it will be optimized as follows:

vmovapd 48(%rsp), %xmm0
vmovapd 32(%rsp), %xmm1
vmovapd 16(%rsp), %xmm2
kmovw %eax, %k1
vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1} {z} # xmm0 = (xmm1 * xmm0) + xmm2

The upper 64 bit of the result isn't right.

[pengfei]

Doesn't the modifier {z} clean the upper 64 bits?

[LiuChen3]

In D75506#1902544, @pengfei wrote:

Doesn't the modifier {z} clean the upper 64 bits?

DEST[127:63] should be unchanged. In the example, the upper 64bit should be upper 64 bit of 16(%rsp).

[RKSimon]

test case ?

[LiuChen3]

Has been correctly fix by D75526 .

llvm/lib/Target/X86/X86InstrAVX512.td

defm VFNMSUB132   : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86any_Fnmsub,
                                        X86Fnmsub, X86FnmsubRnd>;
 
 // Scalar FMA
 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                                dag RHS_r, dag RHS_m, dag RHS_b, bit MaskOnlyReg> {
 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
   defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
-          "$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
+          "$src3, $src2", "$src2, $src3", (null_frag)>,
           AVX512FMA3Base, Sched<[SchedWriteFMA.Scl]>, SIMD_EXC;
 
   let mayLoad = 1 in
   defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
-          "$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
+          "$src3, $src2", "$src2, $src3", (null_frag)>,
           AVX512FMA3Base, Sched<[SchedWriteFMA.Scl.Folded, SchedWriteFMA.Scl.ReadAfterFold]>, SIMD_EXC;
 
   let Uses = [MXCSR] in
   defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
          (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
-         OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (null_frag), 1, 1>,
+         OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (null_frag)>,
          AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[SchedWriteFMA.Scl]>;
 
   let isCodeGenOnly = 1, isCommutable = 1 in {
     def r     : AVX512FMA3S<opc, MRMSrcReg, (outs _.FRC:$dst),
                      (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
                      !strconcat(OpcodeStr,
                               "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
                      !if(MaskOnlyReg, [], [RHS_r])>, Sched<[SchedWriteFMA.Scl]>, SIMD_EXC;