[ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

[dmgreen]

Summary

The ASRL/LSRL long shifts are generated from 64bit shifts. Once we have them, it might turn out that enough of the 64bit result was not required that we can use a smaller shift to perform the same result. As the smaller shift can in general be folded in more way, such as into add instructions in one of the test cases here, we can use the demand bit analysis to prefer the smaller shifts where we can.

[samparker]

Are there tests for shifts greater than 31? And don't we do some weird stuff with negative shifts, or is that just with custom nodes?

llvm/lib/Target/ARM/ARMISelLowering.h

362

Doesn't this need override?

[dmgreen]

Whoops. That was the wrong number on that commit.

[dmgreen]

Rebase to on top of D75553 (I had not really considered them together when I wrote that, only from the times we would generate the nodes from shifts. From intrinsics more cases can come up). It makes sense to do that one first as this has become more complex.

I have tried to add a few of the obvious cases that I thought might come up, when parts of the shift are not used. The intrinsics are really designed for variable shifts but they can become constant during optimisation (and the first example I saw of someone using them was asrl(X, 23), as opposed to using a standard shift).

This doesn't feel like the prettiest code I've ever written. Suggestions welcome.

[samparker]

llvm/lib/Target/ARM/ARMISelLowering.cpp

14184

For readability, maybe introduce a lambda to help create the shift and do the replacement? Some aptly named variables for shift ranges and whether we're doing a logical/left/right shift could also help.

[dmgreen]

I decided that this was really doing two separate things, and should split it back in two. This it the first (not so ugly) part for the time being. I will try to get to the second part later.

[samparker]

Simplified the simplify! LGTM

[dmgreen]

Thanks

llvm/lib/Target/ARM/ARMISelLowering.h

public:
     void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                        SDNode *Node) const override;
 
     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
+    bool SimplifyDemandedBitsForTargetNode(SDValue Op,
+                                           const APInt &OriginalDemandedBits,
+                                           const APInt &OriginalDemandedElts,
+                                           KnownBits &Known,
+                                           TargetLoweringOpt &TLO,
+                                           unsigned Depth) const override;
+
     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
 
     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
     /// unaligned memory accesses of the specified type. Returns whether it
     /// is "fast" by reference in the second argument.
     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
                                         unsigned Align,
                                         MachineMemOperand::Flags Flags,

llvm/lib/Target/ARM/ARMISelLowering.cpp

 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
   switch (IntNo) {
   default:
     // Don't do anything for most intrinsics.
     break;
 
   // Vector shifts: check for immediate versions and lower them.
   // Note: This is done during DAG combining instead of DAG legalizing because
   // the build_vectors for 64-bit vector element shift counts are generally
   // not legal, and it is hard to see their values after they get legalized to
   // loads from a constant pool.
   case Intrinsic::arm_neon_vshifts:
   case Intrinsic::arm_neon_vshiftu:
   case Intrinsic::arm_neon_vrshifts:
   case Intrinsic::arm_neon_vrshiftu:
   case Intrinsic::arm_neon_vrshiftn:
ARMTargetLowering::targetShrinkDemandedConstant(SDValue Op,
   // We could try to recognize lsls+lsrs or lsrs+lsls pairs here.
   // We could try to prefer Thumb1 immediates which can be lowered to a
   // two-instruction sequence.
   // We could try to recognize more legal ARM/Thumb2 immediates here.
 
   return false;
 }
 
+bool ARMTargetLowering::SimplifyDemandedBitsForTargetNode(
+    SDValue Op, const APInt &OriginalDemandedBits,
+    const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
+    unsigned Depth) const {
+  unsigned Opc = Op.getOpcode();
+
+  switch (Opc) {
+  case ARMISD::ASRL:
+  case ARMISD::LSRL: {
+    // If this is result 0 and the other result is unused, see if the demand
+    // bits allow us to shrink this long shift into a standard small shift in
+    // the opposite direction.
+    if (Op.getResNo() == 0 && !Op->hasAnyUseOfValue(1) &&
+        isa<ConstantSDNode>(Op->getOperand(2))) {
+      unsigned ShAmt = Op->getConstantOperandVal(2);
+      if (ShAmt < 32 && OriginalDemandedBits.isSubsetOf(
+                            APInt::getAllOnesValue(32) << (32 - ShAmt)))
+        return TLO.CombineTo(
+            Op, TLO.DAG.getNode(
+                    ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1),
+                    TLO.DAG.getConstant(32 - ShAmt, SDLoc(Op), MVT::i32)));
+    }
+    break;
+  }
+  }
+
+  return TargetLowering::SimplifyDemandedBitsForTargetNode(
+      Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
+}
 
 //===----------------------------------------------------------------------===//
 //                           ARM Inline Assembly Support
 //===----------------------------------------------------------------------===//
 
 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
   // Looking for "rev" which is V6+.
   if (!Subtarget->hasV6Ops())

llvm/test/CodeGen/Thumb2/fir.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
 ; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NOMVE
 
 define void @test1(i32* %p0, i32 *%p1, i32 *%p2, i32 *%pDst) {
-; CHECK-MVE-LABEL: test1:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    ldr r1, [r1]
-; CHECK-MVE-NEXT:    ldr r2, [r2]
-; CHECK-MVE-NEXT:    ldr r0, [r0]
-; CHECK-MVE-NEXT:    smull r2, r1, r2, r1
-; CHECK-MVE-NEXT:    lsrl r2, r1, #31
-; CHECK-MVE-NEXT:    bic r1, r2, #1
-; CHECK-MVE-NEXT:    add r0, r1
-; CHECK-MVE-NEXT:    str r0, [r3]
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-NOMVE-LABEL: test1:
-; CHECK-NOMVE:       @ %bb.0: @ %entry
-; CHECK-NOMVE-NEXT:    ldr r1, [r1]
-; CHECK-NOMVE-NEXT:    ldr r2, [r2]
-; CHECK-NOMVE-NEXT:    ldr r0, [r0]
-; CHECK-NOMVE-NEXT:    smmul r1, r2, r1
-; CHECK-NOMVE-NEXT:    add.w r0, r0, r1, lsl #1
-; CHECK-NOMVE-NEXT:    str r0, [r3]
-; CHECK-NOMVE-NEXT:    bx lr
+; CHECK-LABEL: test1:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    ldr r1, [r1]
+; CHECK-NEXT:    ldr r2, [r2]
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    smmul r1, r2, r1
+; CHECK-NEXT:    add.w r0, r0, r1, lsl #1
+; CHECK-NEXT:    str r0, [r3]
+; CHECK-NEXT:    bx lr
 entry:
   %l3 = load i32, i32* %p0, align 4
   %l4 = load i32, i32* %p1, align 4
   %conv5.us = sext i32 %l4 to i64
   %l5 = load i32, i32* %p2, align 4
   %conv6.us = sext i32 %l5 to i64
   %mul.us = mul nsw i64 %conv6.us, %conv5.us
   %l6 = lshr i64 %mul.us, 31

llvm/test/CodeGen/Thumb2/shift_parts.ll

 entry:
   %shr = shl i64 %x, 44
   %t = trunc i64 %shr to i32
   ret i32 %t
 }
 
 
 define i32 @ashr_demand_bottommask(i64 %x) {
-; CHECK-MVE-LABEL: ashr_demand_bottommask:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    lsrl r0, r1, #31
-; CHECK-MVE-NEXT:    bic r0, r0, #1
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-NON-MVE-LABEL: ashr_demand_bottommask:
-; CHECK-NON-MVE:       @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT:    lsls r0, r1, #1
-; CHECK-NON-MVE-NEXT:    bx lr
+; CHECK-LABEL: ashr_demand_bottommask:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    lsls r0, r1, #1
+; CHECK-NEXT:    bx lr
 entry:
   %shr = ashr i64 %x, 31
   %t = trunc i64 %shr to i32
   %a = and i32 %t, -2
   ret i32 %a
 }
 
 define i32 @lshr_demand_bottommask(i64 %x) {
-; CHECK-MVE-LABEL: lshr_demand_bottommask:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    lsrl r0, r1, #31
-; CHECK-MVE-NEXT:    bic r0, r0, #1
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-NON-MVE-LABEL: lshr_demand_bottommask:
-; CHECK-NON-MVE:       @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT:    lsls r0, r1, #1
-; CHECK-NON-MVE-NEXT:    bx lr
+; CHECK-LABEL: lshr_demand_bottommask:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    lsls r0, r1, #1
+; CHECK-NEXT:    bx lr
 entry:
   %shr = lshr i64 %x, 31
   %t = trunc i64 %shr to i32
   %a = and i32 %t, -2
   ret i32 %a
 }
 
 define i32 @lsl_demand_bottommask(i64 %x) {
 ; CHECK-LABEL: lsl_demand_bottommask:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    lsls r0, r0, #31
 ; CHECK-NEXT:    bx lr
 entry:
   %shr = shl i64 %x, 31
   %t = trunc i64 %shr to i32
   %a = and i32 %t, -2
   ret i32 %a
 }
 
 define i32 @ashr_demand_bottommask2(i64 %x) {
-; CHECK-MVE-LABEL: ashr_demand_bottommask2:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    lsrl r0, r1, #31
-; CHECK-MVE-NEXT:    bic r0, r0, #3
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-NON-MVE-LABEL: ashr_demand_bottommask2:
-; CHECK-NON-MVE:       @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT:    mvn r0, #2
-; CHECK-NON-MVE-NEXT:    and.w r0, r0, r1, lsl #1
-; CHECK-NON-MVE-NEXT:    bx lr
+; CHECK-LABEL: ashr_demand_bottommask2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mvn r0, #2
+; CHECK-NEXT:    and.w r0, r0, r1, lsl #1
+; CHECK-NEXT:    bx lr
 entry:
   %shr = ashr i64 %x, 31
   %t = trunc i64 %shr to i32
   %a = and i32 %t, -4
   ret i32 %a
 }
 
 define i32 @lshr_demand_bottommask2(i64 %x) {
-; CHECK-MVE-LABEL: lshr_demand_bottommask2:
-; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    lsrl r0, r1, #31
-; CHECK-MVE-NEXT:    bic r0, r0, #3
-; CHECK-MVE-NEXT:    bx lr
-;
-; CHECK-NON-MVE-LABEL: lshr_demand_bottommask2:
-; CHECK-NON-MVE:       @ %bb.0: @ %entry
-; CHECK-NON-MVE-NEXT:    mvn r0, #2
-; CHECK-NON-MVE-NEXT:    and.w r0, r0, r1, lsl #1
-; CHECK-NON-MVE-NEXT:    bx lr
+; CHECK-LABEL: lshr_demand_bottommask2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mvn r0, #2
+; CHECK-NEXT:    and.w r0, r0, r1, lsl #1
+; CHECK-NEXT:    bx lr
 entry:
   %shr = lshr i64 %x, 31
   %t = trunc i64 %shr to i32
   %a = and i32 %t, -4
   ret i32 %a
 }
 
 define i32 @lsl_demand_bottommask2(i64 %x) {