[ARM][Thumb2] Support .w assembler qualifier for pld/pldw/pli

[falstaff84]

Summary

Accept explicit wide assembler qualifier for the pld/pldw/pli.

[ostannard]

LGTM

[psmith]

The change looks good to me, but I'm far from an expert on tablegen. There is a similar revision for ldrb.w under D68916 I've added reviewers that have been involved there to see if they have any thoughts on the approach.

[psmith]

ps. I'm quite happy, with ostannard approving.

[falstaff84]

Thanks for the review. I do not have commit access, so I would be glad if somebody could merge that for me.

[ostannard]

I've committed this and D75143 for you.

llvm/lib/Target/ARM/ARMInstrThumb2.td

def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
     let DecoderMethod = "DecodeT2LoadShift";
   }
 }
 
 defm t2PLD    : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
 defm t2PLDW   : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
 defm t2PLI    : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
 
+// PLD/PLDW/PLI aliases w/ the optional .w suffix
+def : t2InstAlias<"pld${p}.w\t$addr",
+                 (t2PLDi12  t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"pld${p}.w\t$addr",
+                 (t2PLDi8   t2addrmode_negimm8:$addr, pred:$p)>;
+def : t2InstAlias<"pld${p}.w\t$addr",
+                 (t2PLDs    t2addrmode_so_reg:$addr, pred:$p)>;
+
+def : InstAlias<"pldw${p}.w\t$addr",
+                 (t2PLDWi12  t2addrmode_imm12:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7,HasMP]>;
+def : InstAlias<"pldw${p}.w\t$addr",
+                 (t2PLDWi8   t2addrmode_negimm8:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7,HasMP]>;
+def : InstAlias<"pldw${p}.w\t$addr",
+                 (t2PLDWs    t2addrmode_so_reg:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7,HasMP]>;
+
+def : InstAlias<"pli${p}.w\t$addr",
+                 (t2PLIi12  t2addrmode_imm12:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+def : InstAlias<"pli${p}.w\t$addr",
+                 (t2PLIi8   t2addrmode_negimm8:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+def : InstAlias<"pli${p}.w\t$addr",
+                 (t2PLIs    t2addrmode_so_reg:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+
 // pci variant is very similar to i12, but supports negative offsets
 // from the PC. Only PLD and PLI have pci variants (not PLDW)
 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
                IIC_Preload, opc, "\t$addr",
                [(ARMPreload (ARMWrapper tconstpool:$addr),
                 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
   let Inst{31-25} = 0b1111100;
   let Inst{24} = inst;
   let Inst{22-20} = 0b001;
   let Inst{19-16} = 0b1111;
   let Inst{15-12} = 0b1111;
 
   bits<13> addr;
   let Inst{23}   = addr{12};   // add = (U == '1')
   let Inst{11-0} = addr{11-0}; // imm12
 
   let DecoderMethod = "DecodeT2LoadLabel";
 }
 
 def t2PLDpci : T2Iplpci<0, "pld">,  Requires<[IsThumb2]>;
 def t2PLIpci : T2Iplpci<1, "pli">,  Requires<[IsThumb2,HasV7]>;
 
+def : t2InstAlias<"pld${p}.w $addr",
+                  (t2PLDpci t2ldrlabel:$addr, pred:$p)>;
+def : InstAlias<"pli${p}.w $addr",
+                 (t2PLIpci  t2ldrlabel:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+
+// PLD/PLI with alternate literal form.
+def : t2InstAlias<"pld${p} $addr",
+                  (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
+def : InstAlias<"pli${p} $addr",
+                 (t2PLIpci  t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+def : t2InstAlias<"pld${p}.w $addr",
+                  (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
+def : InstAlias<"pli${p}.w $addr",
+                 (t2PLIpci  t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
+      Requires<[IsThumb2,HasV7]>;
+
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
 //
 
 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
                             InstrItinClass itin_upd, bit L_bit> {
   def IA :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),

 def t2LDRConstPool
   : t2AsmPseudo<"ldr${p} $Rt, $immediate",
                 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
 // Version w/ the .w suffix.
 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
                   (t2LDRConstPool GPRnopc:$Rt,
                   const_pool_asm_imm:$immediate, pred:$p)>;
 
-// PLD/PLDW/PLI with alternate literal form.
-def : t2InstAlias<"pld${p} $addr",
-                  (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
-def : InstAlias<"pli${p} $addr",
-                 (t2PLIpci  t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
-      Requires<[IsThumb2,HasV7]>;
-
-
 //===----------------------------------------------------------------------===//
 // ARMv8.1m instructions
 //
 
 class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
              string ops, string cstr, list<dag> pattern>
   : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr,
              pattern>,

llvm/test/MC/ARM/basic-thumb2-instructions.s

 @------------------------------------------------------------------------------
         pld [r5, #-4]
         pld [r6, #32]
         pld [r6, #33]
         pld [r6, #257]
         pld [r7, #257]
         pld [r1, #0]
         pld [r1, #-0]
+        pld.w [r1, #-0]
 
 @ CHECK: pld  [r5, #-4]               @ encoding: [0x15,0xf8,0x04,0xfc]
 @ CHECK: pld  [r6, #32]               @ encoding: [0x96,0xf8,0x20,0xf0]
 @ CHECK: pld  [r6, #33]               @ encoding: [0x96,0xf8,0x21,0xf0]
 @ CHECK: pld  [r6, #257]              @ encoding: [0x96,0xf8,0x01,0xf1]
 @ CHECK: pld  [r7, #257]              @ encoding: [0x97,0xf8,0x01,0xf1]
 @ CHECK: pld  [r1]                    @ encoding: [0x91,0xf8,0x00,0xf0]
 @ CHECK: pld  [r1, #-0]               @ encoding: [0x11,0xf8,0x00,0xfc]
+@ CHECK: pld  [r1, #-0]               @ encoding: [0x11,0xf8,0x00,0xfc]
 
 
 @------------------------------------------------------------------------------
 @ PLD(literal)
 @------------------------------------------------------------------------------
 @        pld  _foo
 
 @ FIXME: pld  _foo                    @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
             @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
 
         pld [pc,#-4095]
+        pld.w [pc,#-4095]
+@ CHECK: pld [pc, #-4095]            @ encoding: [0x1f,0xf8,0xff,0xff]
 @ CHECK: pld [pc, #-4095]            @ encoding: [0x1f,0xf8,0xff,0xff]
 
 
 @------------------------------------------------------------------------------
 @ PLD(register)
 @------------------------------------------------------------------------------
         pld [r8, r1]
         pld [r5, r2]
+        pld.w [r5, r2]
         pld [r0, r2, lsl #3]
         pld [r8, r2, lsl #2]
         pld [sp, r2, lsl #1]
         pld [sp, r2, lsl #0]
+        pld.w [sp, r2, lsl #1]
 
 @ CHECK: pld  [r8, r1]                @ encoding: [0x18,0xf8,0x01,0xf0]
 @ CHECK: pld  [r5, r2]                @ encoding: [0x15,0xf8,0x02,0xf0]
+@ CHECK: pld  [r5, r2]                @ encoding: [0x15,0xf8,0x02,0xf0]
 @ CHECK: pld  [r0, r2, lsl #3]        @ encoding: [0x10,0xf8,0x32,0xf0]
 @ CHECK: pld  [r8, r2, lsl #2]        @ encoding: [0x18,0xf8,0x22,0xf0]
 @ CHECK: pld  [sp, r2, lsl #1]        @ encoding: [0x1d,0xf8,0x12,0xf0]
 @ CHECK: pld  [sp, r2]                @ encoding: [0x1d,0xf8,0x02,0xf0]
+@ CHECK: pld  [sp, r2, lsl #1]        @ encoding: [0x1d,0xf8,0x12,0xf0]
 
 @------------------------------------------------------------------------------
 @ PLI(immediate)
 @------------------------------------------------------------------------------
         pli [r5, #-4]
         pli [r6, #32]
         pli [r6, #33]
         pli [r6, #257]
         pli [r7, #257]
         pli [pc, #+4095]
         pli [pc, #-4095]
+        pli.w [pc, #-4095]
 
 @ CHECK: pli  [r5, #-4]               @ encoding: [0x15,0xf9,0x04,0xfc]
 @ CHECK: pli  [r6, #32]               @ encoding: [0x96,0xf9,0x20,0xf0]
 @ CHECK: pli  [r6, #33]               @ encoding: [0x96,0xf9,0x21,0xf0]
 @ CHECK: pli  [r6, #257]              @ encoding: [0x96,0xf9,0x01,0xf1]
 @ CHECK: pli  [r7, #257]              @ encoding: [0x97,0xf9,0x01,0xf1]
 @ CHECK: pli    [pc, #4095]             @ encoding: [0x9f,0xf9,0xff,0xff]
 @ CHECK: pli    [pc, #-4095]            @ encoding: [0x1f,0xf9,0xff,0xff]
+@ CHECK: pli    [pc, #-4095]            @ encoding: [0x1f,0xf9,0xff,0xff]
 
 
 @------------------------------------------------------------------------------
 @ PLI(literal)
 @------------------------------------------------------------------------------
 @        pli  _foo
 
 
 @ FIXME: pli  _foo                    @ encoding: [0x9f'A',0xf9'A',A,0xf0'A']
            @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
 
 
 @------------------------------------------------------------------------------
 @ PLI(register)
 @------------------------------------------------------------------------------
         pli [r8, r1]
         pli [r5, r2]
+        pli.w [r5, r2]
         pli [r0, r2, lsl #3]
         pli [r8, r2, lsl #2]
         pli [sp, r2, lsl #1]
         pli [sp, r2, lsl #0]
+        pli.w [sp, r2, lsl #1]
 
 @ CHECK: pli  [r8, r1]                @ encoding: [0x18,0xf9,0x01,0xf0]
 @ CHECK: pli  [r5, r2]                @ encoding: [0x15,0xf9,0x02,0xf0]
+@ CHECK: pli  [r5, r2]                @ encoding: [0x15,0xf9,0x02,0xf0]
 @ CHECK: pli  [r0, r2, lsl #3]        @ encoding: [0x10,0xf9,0x32,0xf0]
 @ CHECK: pli  [r8, r2, lsl #2]        @ encoding: [0x18,0xf9,0x22,0xf0]
 @ CHECK: pli  [sp, r2, lsl #1]        @ encoding: [0x1d,0xf9,0x12,0xf0]
 @ CHECK: pli  [sp, r2]                @ encoding: [0x1d,0xf9,0x02,0xf0]
+@ CHECK: pli  [sp, r2, lsl #1]        @ encoding: [0x1d,0xf9,0x12,0xf0]
 
 @------------------------------------------------------------------------------
 @ POP (alias)
 @------------------------------------------------------------------------------
         pop {r2, r9}
 
 @ CHECK: pop.w  {r2, r9}                @ encoding: [0xbd,0xe8,0x04,0x02]