This is an archive of the discontinued LLVM Phabricator instance.

Differential D75078

AMDGPU/GlobalISel: Improve handling of illegal return types
ClosedPublic

Authored by arsenm on Feb 24 2020, 1:53 PM.

Details

Reviewers
nhaehnle
kerbowa
foad
Summary

Most importantly, this fixes ret i8. Also make sure to handle
signext/zeroext for odd types > i32. Some of the corresponding
argument passing fixes also need to be handled.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
8 lines
84 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
312 lines

Diff 246296

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

Show All 24 Lines
class AMDGPUCallLowering: public CallLowering { class AMDGPUCallLowering: public CallLowering {
Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy, Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy,
uint64_t Offset) const; uint64_t Offset) const;
void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset, void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
unsigned Align, Register DstReg) const; unsigned Align, Register DstReg) const;
/// A function of this type is used to perform value split action. /// A function of this type is used to perform value split action.
using SplitArgTy = std::function<void(ArrayRef<Register>, LLT, LLT, int)>; using SplitArgTy = std::function<void(ArrayRef<Register>, Register, LLT, LLT, int)>;
void splitToValueTypes(const ArgInfo &OrigArgInfo, void splitToValueTypes(MachineIRBuilder &B,
const ArgInfo &OrigArgInfo,
unsigned OrigArgIdx,
SmallVectorImpl<ArgInfo> &SplitArgs, SmallVectorImpl<ArgInfo> &SplitArgs,
const DataLayout &DL, MachineRegisterInfo &MRI, const DataLayout &DL,
CallingConv::ID CallConv, CallingConv::ID CallConv,
SplitArgTy SplitArg) const; SplitArgTy SplitArg) const;
bool lowerReturnVal(MachineIRBuilder &B, const Value *Val, bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const; ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
public: public:
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI); AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
Show All 14 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
}; };
} }
AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
: CallLowering(&TLI) { : CallLowering(&TLI) {
} }
// FIXME: Compatability shim
static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
switch (MIOpc) {
case TargetOpcode::G_SEXT:
return ISD::SIGN_EXTEND;
case TargetOpcode::G_ZEXT:
return ISD::ZERO_EXTEND;
case TargetOpcode::G_ANYEXT:
return ISD::ANY_EXTEND;
default:
llvm_unreachable("not an extend opcode");
}
}
void AMDGPUCallLowering::splitToValueTypes( void AMDGPUCallLowering::splitToValueTypes(
const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, MachineIRBuilder &B,
const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv, const ArgInfo &OrigArg, unsigned OrigArgIdx,
SmallVectorImpl<ArgInfo> &SplitArgs,
const DataLayout &DL, CallingConv::ID CallConv,
SplitArgTy PerformArgSplit) const { SplitArgTy PerformArgSplit) const {
const SITargetLowering &TLI = *getTLI<SITargetLowering>(); const SITargetLowering &TLI = *getTLI<SITargetLowering>();
LLVMContext &Ctx = OrigArg.Ty->getContext(); LLVMContext &Ctx = OrigArg.Ty->getContext();
if (OrigArg.Ty->isVoidTy()) if (OrigArg.Ty->isVoidTy())
return; return;
SmallVector<EVT, 4> SplitVTs; SmallVector<EVT, 4> SplitVTs;
ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs); ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs);
assert(OrigArg.Regs.size() == SplitVTs.size()); assert(OrigArg.Regs.size() == SplitVTs.size());
int SplitIdx = 0; int SplitIdx = 0;
for (EVT VT : SplitVTs) { for (EVT VT : SplitVTs) {
unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CallConv, VT); Register Reg = OrigArg.Regs[SplitIdx];
Type *Ty = VT.getTypeForEVT(Ctx); Type *Ty = VT.getTypeForEVT(Ctx);
LLT LLTy = getLLTForType(*Ty, DL);
if (OrigArgIdx == AttributeList::ReturnIndex && VT.isScalarInteger()) {
unsigned ExtendOp = TargetOpcode::G_ANYEXT;
if (OrigArg.Flags[0].isSExt()) {
assert(OrigArg.Regs.size() == 1 && "expect only simple return values");
ExtendOp = TargetOpcode::G_SEXT;
} else if (OrigArg.Flags[0].isZExt()) {
assert(OrigArg.Regs.size() == 1 && "expect only simple return values");
ExtendOp = TargetOpcode::G_ZEXT;
}
EVT ExtVT = TLI.getTypeForExtReturn(Ctx, VT,
extOpcodeToISDExtOpcode(ExtendOp));
if (ExtVT != VT) {
VT = ExtVT;
Ty = ExtVT.getTypeForEVT(Ctx);
LLTy = getLLTForType(*Ty, DL);
Reg = B.buildInstr(ExtendOp, {LLTy}, {Reg}).getReg(0);
}
}
unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CallConv, VT);
MVT RegVT = TLI.getRegisterTypeForCallingConv(Ctx, CallConv, VT);
if (NumParts == 1) { if (NumParts == 1) {
// No splitting to do, but we want to replace the original type (e.g. [1 x // No splitting to do, but we want to replace the original type (e.g. [1 x
// double] -> double). // double] -> double).
SplitArgs.emplace_back(OrigArg.Regs[SplitIdx], Ty, SplitArgs.emplace_back(Reg, Ty, OrigArg.Flags, OrigArg.IsFixed);
OrigArg.Flags, OrigArg.IsFixed);
++SplitIdx; ++SplitIdx;
continue; continue;
} }
LLT LLTy = getLLTForType(*Ty, DL);
SmallVector<Register, 8> SplitRegs; SmallVector<Register, 8> SplitRegs;
Type *PartTy = EVT(RegVT).getTypeForEVT(Ctx);
EVT PartVT = TLI.getRegisterTypeForCallingConv(Ctx, CallConv, VT);
Type *PartTy = PartVT.getTypeForEVT(Ctx);
LLT PartLLT = getLLTForType(*PartTy, DL); LLT PartLLT = getLLTForType(*PartTy, DL);
MachineRegisterInfo &MRI = *B.getMRI();
// FIXME: Should we be reporting all of the part registers for a single // FIXME: Should we be reporting all of the part registers for a single
// argument, and let handleAssignments take care of the repacking? // argument, and let handleAssignments take care of the repacking?
for (unsigned i = 0; i < NumParts; ++i) { for (unsigned i = 0; i < NumParts; ++i) {
Register PartReg = MRI.createGenericVirtualRegister(PartLLT); Register PartReg = MRI.createGenericVirtualRegister(PartLLT);
SplitRegs.push_back(PartReg); SplitRegs.push_back(PartReg);
SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags); SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags);
} }
PerformArgSplit(SplitRegs, LLTy, PartLLT, SplitIdx); PerformArgSplit(SplitRegs, Reg, LLTy, PartLLT, SplitIdx);
++SplitIdx; ++SplitIdx;
} }
} }
// Get the appropriate type to make \p OrigTy \p Factor times bigger. // Get the appropriate type to make \p OrigTy \p Factor times bigger.
static LLT getMultipleType(LLT OrigTy, int Factor) { static LLT getMultipleType(LLT OrigTy, int Factor) {
if (OrigTy.isVector()) { if (OrigTy.isVector()) {
return LLT::vector(OrigTy.getNumElements() * Factor, return LLT::vector(OrigTy.getNumElements() * Factor,
OrigTy.getElementType()); OrigTy.getElementType());
} }
return LLT::scalar(OrigTy.getSizeInBits() * Factor); return LLT::scalar(OrigTy.getSizeInBits() * Factor);
} }
// TODO: Move to generic code // TODO: Move to generic code
static void unpackRegsToOrigType(MachineIRBuilder &B, static void unpackRegsToOrigType(MachineIRBuilder &B,
ArrayRef<Register> DstRegs, ArrayRef<Register> DstRegs,
Register SrcReg, Register SrcReg,
const CallLowering::ArgInfo &Info,
LLT SrcTy, LLT SrcTy,
LLT PartTy) { LLT PartTy) {
assert(DstRegs.size() > 1 && "Nothing to unpack"); assert(DstRegs.size() > 1 && "Nothing to unpack");
const unsigned SrcSize = SrcTy.getSizeInBits(); const unsigned SrcSize = SrcTy.getSizeInBits();
const unsigned PartSize = PartTy.getSizeInBits(); const unsigned PartSize = PartTy.getSizeInBits();
if (SrcTy.isVector() && !PartTy.isVector() && if (SrcTy.isVector() && !PartTy.isVector() &&
Show All 29 Linesbool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
const Value *Val, ArrayRef<Register> VRegs, const Value *Val, ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const { MachineInstrBuilder &Ret) const {
if (!Val) if (!Val)
return true; return true;
auto &MF = B.getMF(); auto &MF = B.getMF();
const auto &F = MF.getFunction(); const auto &F = MF.getFunction();
const DataLayout &DL = MF.getDataLayout(); const DataLayout &DL = MF.getDataLayout();
MachineRegisterInfo *MRI = B.getMRI();
CallingConv::ID CC = F.getCallingConv(); CallingConv::ID CC = F.getCallingConv();
const SITargetLowering &TLI = *getTLI<SITargetLowering>(); const SITargetLowering &TLI = *getTLI<SITargetLowering>();
MachineRegisterInfo &MRI = MF.getRegInfo();
ArgInfo OrigRetInfo(VRegs, Val->getType()); ArgInfo OrigRetInfo(VRegs, Val->getType());
setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F); setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
SmallVector<ArgInfo, 4> SplitRetInfos; SmallVector<ArgInfo, 4> SplitRetInfos;
splitToValueTypes( splitToValueTypes(
OrigRetInfo, SplitRetInfos, DL, MRI, CC, B, OrigRetInfo, AttributeList::ReturnIndex, SplitRetInfos, DL, CC,
[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { [&](ArrayRef<Register> Regs, Register SrcReg, LLT LLTy, LLT PartLLT,
unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); int VTSplitIdx) {
unpackRegsToOrigType(B, Regs, SrcReg,
SplitRetInfos[VTSplitIdx],
LLTy, PartLLT);
}); });
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg()); CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
OutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn);
OutgoingValueHandler RetHandler(B, MF.getRegInfo(), Ret, AssignFn);
return handleAssignments(B, SplitRetInfos, RetHandler); return handleAssignments(B, SplitRetInfos, RetHandler);
} }
bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B,
const Value *Val, const Value *Val,
ArrayRef<Register> VRegs) const { ArrayRef<Register> VRegs) const {
MachineFunction &MF = B.getMF(); MachineFunction &MF = B.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MFI->setIfReturnsVoid(!Val); MFI->setIfReturnsVoid(!Val);
assert(!Val == VRegs.empty() && "Return value without a vreg"); assert(!Val == VRegs.empty() && "Return value without a vreg");
CallingConv::ID CC = B.getMF().getFunction().getCallingConv(); CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
const bool IsShader = AMDGPU::isShader(CC); const bool IsShader = AMDGPU::isShader(CC);
const bool IsWaveEnd = (IsShader && MFI->returnsVoid()) || const bool IsWaveEnd = (IsShader && MFI->returnsVoid()) ||
AMDGPU::isKernel(CC); AMDGPU::isKernel(CC);
if (IsWaveEnd) { if (IsWaveEnd) {
B.buildInstr(AMDGPU::S_ENDPGM) B.buildInstr(AMDGPU::S_ENDPGM)
.addImm(0); .addImm(0);
return true; return true;
} }
auto const &ST = B.getMF().getSubtarget<GCNSubtarget>(); auto const &ST = MF.getSubtarget<GCNSubtarget>();
unsigned ReturnOpc = unsigned ReturnOpc =
IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return; IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return;
auto Ret = B.buildInstrNoInsert(ReturnOpc); auto Ret = B.buildInstrNoInsert(ReturnOpc);
Register ReturnAddrVReg; Register ReturnAddrVReg;
if (ReturnOpc == AMDGPU::S_SETPC_B64_return) { if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass); ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
▲ Show 20 Lines • Show All 314 Lines • ▼ Show 20 Lines if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
B.buildUndef(VRegs[Idx][I]); B.buildUndef(VRegs[Idx][I]);
++Idx; ++Idx;
continue; continue;
} }
} }
ArgInfo OrigArg(VRegs[Idx], Arg.getType()); ArgInfo OrigArg(VRegs[Idx], Arg.getType());
setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F); const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
setArgFlags(OrigArg, OrigArgIdx, DL, F);
splitToValueTypes( splitToValueTypes(
OrigArg, SplitArgs, DL, MRI, CC, B, OrigArg, OrigArgIdx, SplitArgs, DL, CC,
// FIXME: We should probably be passing multiple registers to // FIXME: We should probably be passing multiple registers to
// handleAssignments to do this // handleAssignments to do this
[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { [&](ArrayRef<Register> Regs, Register DstReg,
LLT LLTy, LLT PartLLT, int VTSplitIdx) {
assert(DstReg == VRegs[Idx][VTSplitIdx]);
packSplitRegsToOrigType(B, VRegs[Idx][VTSplitIdx], Regs, packSplitRegsToOrigType(B, VRegs[Idx][VTSplitIdx], Regs,
LLTy, PartLLT); LLTy, PartLLT);
}); });
++Idx; ++Idx;
} }
// At least one interpolation mode must be enabled or else the GPU will // At least one interpolation mode must be enabled or else the GPU will
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

Show All 40 Linesdefine signext i1 @i1_signext_func_void() #0 {
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s1) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s1)
; CHECK: $vgpr0 = COPY [[SEXT]](s32) ; CHECK: $vgpr0 = COPY [[SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0 ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i1, i1 addrspace(1)* undef %val = load i1, i1 addrspace(1)* undef
ret i1 %val ret i1 %val
} }
define i7 @i7_func_void() #0 {
; CHECK-LABEL: name: i7_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s7) = G_LOAD [[DEF]](p1) :: (load 1 from `i7 addrspace(1)* undef`, addrspace 1)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s7)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i7, i7 addrspace(1)* undef
ret i7 %val
}
define zeroext i7 @i7_zeroext_func_void() #0 {
; CHECK-LABEL: name: i7_zeroext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s7) = G_LOAD [[DEF]](p1) :: (load 1 from `i7 addrspace(1)* undef`, addrspace 1)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s7)
; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i7, i7 addrspace(1)* undef
ret i7 %val
}
define signext i7 @i7_signext_func_void() #0 {
; CHECK-LABEL: name: i7_signext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s7) = G_LOAD [[DEF]](p1) :: (load 1 from `i7 addrspace(1)* undef`, addrspace 1)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s7)
; CHECK: $vgpr0 = COPY [[SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i7, i7 addrspace(1)* undef
ret i7 %val
}
define i8 @i8_func_void() #0 { define i8 @i8_func_void() #0 {
; CHECK-LABEL: name: i8_func_void ; CHECK-LABEL: name: i8_func_void
; CHECK: bb.0: ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i8, i8 addrspace(1)* undef %val = load i8, i8 addrspace(1)* undef
ret i8 %val ret i8 %val
} }
define zeroext i8 @i8_zeroext_func_void() #0 { define zeroext i8 @i8_zeroext_func_void() #0 {
; CHECK-LABEL: name: i8_zeroext_func_void ; CHECK-LABEL: name: i8_zeroext_func_void
; CHECK: bb.0: ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s8)
; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i8, i8 addrspace(1)* undef %val = load i8, i8 addrspace(1)* undef
ret i8 %val ret i8 %val
} }
define signext i8 @i8_signext_func_void() #0 { define signext i8 @i8_signext_func_void() #0 {
; CHECK-LABEL: name: i8_signext_func_void ; CHECK-LABEL: name: i8_signext_func_void
; CHECK: bb.0: ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s8)
; CHECK: $vgpr0 = COPY [[SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
%val = load i8, i8 addrspace(1)* undef %val = load i8, i8 addrspace(1)* undef
ret i8 %val ret i8 %val
} }
define i16 @i16_func_void() #0 { define i16 @i16_func_void() #0 {
; CHECK-LABEL: name: i16_func_void ; CHECK-LABEL: name: i16_func_void
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define i48 @i48_func_void() #0 { define i48 @i48_func_void() #0 {
; CHECK-LABEL: name: i48_func_void ; CHECK-LABEL: name: i48_func_void
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s48)
; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[DEF1]], [[LOAD]](s48), 0 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[INSERT]](s64), 0 ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INSERT]](s64), 32 ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32) ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: $vgpr1 = COPY [[EXTRACT1]](s32) ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
%val = load i48, i48 addrspace(1)* undef, align 8
ret i48 %val
}
define signext i48 @i48_signext_func_void() #0 {
; CHECK-LABEL: name: i48_signext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s48)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
%val = load i48, i48 addrspace(1)* undef, align 8
ret i48 %val
}
define zeroext i48 @i48_zeroext_func_void() #0 {
; CHECK-LABEL: name: i48_zeroext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s48)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
%val = load i48, i48 addrspace(1)* undef, align 8 %val = load i48, i48 addrspace(1)* undef, align 8
ret i48 %val ret i48 %val
} }
define i64 @i64_func_void() #0 { define i64 @i64_func_void() #0 {
; CHECK-LABEL: name: i64_func_void ; CHECK-LABEL: name: i64_func_void
Show All 13 Lines
define i65 @i65_func_void() #0 { define i65 @i65_func_void() #0 {
; CHECK-LABEL: name: i65_func_void ; CHECK-LABEL: name: i65_func_void
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s65) = G_LOAD [[DEF]](p1) :: (load 9 from `i65 addrspace(1)* undef`, align 8, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s65) = G_LOAD [[DEF]](p1) :: (load 9 from `i65 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF ; CHECK: [[ANYEXT:%[0-9]+]]:_(s96) = G_ANYEXT [[LOAD]](s65)
; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[DEF1]], [[LOAD]](s65), 0 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s96)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[INSERT]](s96), 0 ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INSERT]](s96), 32 ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[INSERT]](s96), 64 ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32) ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: $vgpr1 = COPY [[EXTRACT1]](s32) ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
; CHECK: $vgpr2 = COPY [[EXTRACT2]](s32) %val = load i65, i65 addrspace(1)* undef
ret i65 %val
}
define signext i65 @i65_signext_func_void() #0 {
; CHECK-LABEL: name: i65_signext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s65) = G_LOAD [[DEF]](p1) :: (load 9 from `i65 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[SEXT:%[0-9]+]]:_(s96) = G_SEXT [[LOAD]](s65)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s96)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
%val = load i65, i65 addrspace(1)* undef
ret i65 %val
}
define zeroext i65 @i65_zeroext_func_void() #0 {
; CHECK-LABEL: name: i65_zeroext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s65) = G_LOAD [[DEF]](p1) :: (load 9 from `i65 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[ZEXT:%[0-9]+]]:_(s96) = G_ZEXT [[LOAD]](s65)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s96)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
%val = load i65, i65 addrspace(1)* undef %val = load i65, i65 addrspace(1)* undef
ret i65 %val ret i65 %val
} }
define float @f32_func_void() #0 { define float @f32_func_void() #0 {
; CHECK-LABEL: name: f32_func_void ; CHECK-LABEL: name: f32_func_void
▲ Show 20 Lines • Show All 644 Lines • ▼ Show 20 Linesdefine <4 x i8> @v4i8_func_void() #0 {
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%ptr = load volatile <4 x i8> addrspace(1)*, <4 x i8> addrspace(1)* addrspace(4)* undef %ptr = load volatile <4 x i8> addrspace(1)*, <4 x i8> addrspace(1)* addrspace(4)* undef
%val = load <4 x i8>, <4 x i8> addrspace(1)* %ptr %val = load <4 x i8>, <4 x i8> addrspace(1)* %ptr
ret <4 x i8> %val ret <4 x i8> %val
} }
define {i8, i32} @struct_i8_i32_func_void() #0 { define {i8, i32} @struct_i8_i32_func_void() #0 {
; CHECK-LABEL: name: struct_i8_i32_func_void ; CHECK-LABEL: name: struct_i8_i32_func_void
; CHECK: bb.0: ; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `{ i8, i32 } addrspace(1)* undef`, align 4, addrspace 1) ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (load 1 from `{ i8, i32 } addrspace(1)* undef`, align 4, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from `{ i8, i32 } addrspace(1)* undef` + 4, addrspace 1) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from `{ i8, i32 } addrspace(1)* undef` + 4, addrspace 1)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
; CHECK: $vgpr1 = COPY [[LOAD1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
%val = load { i8, i32 }, { i8, i32 } addrspace(1)* undef %val = load { i8, i32 }, { i8, i32 } addrspace(1)* undef
ret { i8, i32 } %val ret { i8, i32 } %val
} }
define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret %arg0) #0 { define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret %arg0) #0 {
; CHECK-LABEL: name: void_func_sret_struct_i8_i32 ; CHECK-LABEL: name: void_func_sret_struct_i8_i32
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Linesdefine void @void_func_sret_max_known_zero_bits(i8 addrspace(5)* sret %arg0) #0 {
%lshr2 = lshr i32 %arg0.int, 18 %lshr2 = lshr i32 %arg0.int, 18
store volatile i32 %lshr0, i32 addrspace(3)* undef store volatile i32 %lshr0, i32 addrspace(3)* undef
store volatile i32 %lshr1, i32 addrspace(3)* undef store volatile i32 %lshr1, i32 addrspace(3)* undef
store volatile i32 %lshr2, i32 addrspace(3)* undef store volatile i32 %lshr2, i32 addrspace(3)* undef
ret void ret void
} }
define i1022 @i1022_func_void() #0 {
; CHECK-LABEL: name: i1022_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s1022) = G_LOAD [[DEF]](p1) :: (load 128 from `i1022 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s1024) = G_ANYEXT [[LOAD]](s1022)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s1024)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)
; CHECK: $vgpr9 = COPY [[UV9]](s32)
; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)
; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)
; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)
; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)
; CHECK: $vgpr20 = COPY [[UV20]](s32)
; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)
; CHECK: $vgpr24 = COPY [[UV24]](s32)
; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: $vgpr31 = COPY [[UV31]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $vgpr31
%val = load i1022, i1022 addrspace(1)* undef
ret i1022 %val
}
define signext i1022 @i1022_signext_func_void() #0 {
; CHECK-LABEL: name: i1022_signext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s1022) = G_LOAD [[DEF]](p1) :: (load 128 from `i1022 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[SEXT:%[0-9]+]]:_(s1024) = G_SEXT [[LOAD]](s1022)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s1024)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)
; CHECK: $vgpr9 = COPY [[UV9]](s32)
; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)
; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)
; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)
; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)
; CHECK: $vgpr20 = COPY [[UV20]](s32)
; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)
; CHECK: $vgpr24 = COPY [[UV24]](s32)
; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: $vgpr31 = COPY [[UV31]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $vgpr31
%val = load i1022, i1022 addrspace(1)* undef
ret i1022 %val
}
define zeroext i1022 @i1022_zeroext_func_void() #0 {
; CHECK-LABEL: name: i1022_zeroext_func_void
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(s1022) = G_LOAD [[DEF]](p1) :: (load 128 from `i1022 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[ZEXT:%[0-9]+]]:_(s1024) = G_ZEXT [[LOAD]](s1022)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s1024)
; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)
; CHECK: $vgpr9 = COPY [[UV9]](s32)
; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)
; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)
; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)
; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)
; CHECK: $vgpr20 = COPY [[UV20]](s32)
; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)
; CHECK: $vgpr24 = COPY [[UV24]](s32)
; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: $vgpr31 = COPY [[UV31]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $vgpr31
%val = load i1022, i1022 addrspace(1)* undef
ret i1022 %val
}
attributes #0 = { nounwind } attributes #0 = { nounwind }