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[mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.
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Authored by hanchung on Feb 19 2020, 2:58 PM.

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hanchung created this revision.Feb 19 2020, 2:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2020, 2:58 PM

This might be wrong. Do we expect to load/store f/i32 instead of spv.array<1 x f/i32 [4]>?

mravishankar requested changes to this revision.Feb 20 2020, 12:54 PM

Might be worth checking that the serialization/deserialization works as well

mlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir
319

Would be good to check the indices here to make sure it is doing spv.AccessChain %arg0[0]

This revision now requires changes to proceed.Feb 20 2020, 12:54 PM
hanchung updated this revision to Diff 245746.Feb 20 2020, 2:21 PM

Load/Store the element type directly, and check the indices for AccessChain.

hanchung marked an inline comment as done.Feb 20 2020, 2:21 PM
mravishankar accepted this revision.Feb 20 2020, 11:44 PM

This looks fine to me. Thanks for adding this.
But please add serialization tests as well

This revision is now accepted and ready to land.Feb 20 2020, 11:44 PM
hanchung updated this revision to Diff 245928.Feb 21 2020, 11:03 AM

Add serialization tests.

This revision was automatically updated to reflect the committed changes.