Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types"

[arsenm]

Summary

This reverts commit b3297ef05179e1fee616b97b1c65b58e4c7fef17.

This change is incorrect. The current semantic of null in the IR is a
pointer with the bitvalue 0. It is not a cast from an integer 0, so
this should preserve the pointer type.

[arsenm]

ping

[aemerson]

Which part of the langref are you referring to?

Anyway, we discussed this internally and this seems slightly better than using inttoptr.

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll

62 ↗

(On Diff #245023)

Could you fix up the selection for arm64 here so we can maintain the existing codegen?

In AArch64InstructionSelector::earlySelect we handle zero values for G_CONSTANT, and we should extend that to handle p0 types to generate the xzr/wzr register forms.

[arsenm]

In D74738#1904305, @aemerson wrote:

Which part of the langref are you referring to?

http://llvm.org/docs/LangRef.html#simple-constants, Null pointer constants. This falls short in actually saying this means a bit-value 0 pointer in all address spaces, but all of the code treats it this way.

Anyway, we discussed this internally and this seems slightly better than using inttoptr.

[arsenm]

ping

[arsenm]

ping

[aemerson]

Could you fix up the ARM64 selection code as I mentioned earlier so we don't generate different instructions?

[arsenm]

Fix AArch64 selection

[aemerson]

LGTM.

[arsenm]

b8fc192d42af56b17b7d940e6c226f4969e0d851

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

 
 bool IRTranslator::translate(const Constant &C, Register Reg) {
   if (auto CI = dyn_cast<ConstantInt>(&C))
     EntryBuilder->buildConstant(Reg, *CI);
   else if (auto CF = dyn_cast<ConstantFP>(&C))
     EntryBuilder->buildFConstant(Reg, *CF);
   else if (isa<UndefValue>(C))
     EntryBuilder->buildUndef(Reg);
-  else if (isa<ConstantPointerNull>(C)) {
-    // As we are trying to build a constant val of 0 into a pointer,
-    // insert a cast to make them correct with respect to types.
-    unsigned NullSize = DL->getTypeSizeInBits(C.getType());
-    auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
-    auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
-    Register ZeroReg = getOrCreateVReg(*ZeroVal);
-    EntryBuilder->buildCast(Reg, ZeroReg);
-  } else if (auto GV = dyn_cast<GlobalValue>(&C))
+  else if (isa<ConstantPointerNull>(C))
+    EntryBuilder->buildConstant(Reg, 0);
+  else if (auto GV = dyn_cast<GlobalValue>(&C))
     EntryBuilder->buildGlobalValue(Reg, GV);
   else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
     if (!CAZ->getType()->isVectorTy())
       return false;
     // Return the scalar if it is a <1 x Ty> vector.
     if (CAZ->getNumElements() == 1)
       return translate(*CAZ->getElementValue(0u), Reg);
     SmallVector<Register, 4> Ops;

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

case TargetOpcode::G_CONSTANT: {
     else if (I.getOperand(1).isImm())
       IsZero = I.getOperand(1).getImm() == 0;
 
     if (!IsZero)
       return false;
 
     Register DefReg = I.getOperand(0).getReg();
     LLT Ty = MRI.getType(DefReg);
-    if (Ty != LLT::scalar(64) && Ty != LLT::scalar(32))
-      return false;
-
-    if (Ty == LLT::scalar(64)) {
+    if (Ty.getSizeInBits() == 64) {
       I.getOperand(1).ChangeToRegister(AArch64::XZR, false);
       RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
-    } else {
+    } else if (Ty.getSizeInBits() == 32) {
       I.getOperand(1).ChangeToRegister(AArch64::WZR, false);
       RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
-    }
+    } else
+      return false;
+
     I.setDesc(TII.get(TargetOpcode::COPY));
     return true;
   }
   default:
     return false;
   }
 }
 

llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

block:
   store i16* %dummy, i16** undef
   ret void
 
 end:
   %vec = load <2 x i16*>, <2 x i16*>* undef
   br label %block
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %3:_(p0), %5:_(s32) (in function: vector_of_pointers_insertelement)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
 define void @vector_of_pointers_insertelement() {
   br label %end
 
 block:
   %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
   store <2 x i16*> %dummy, <2 x i16*>* undef

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
   ; CHECK:   [[C48:%[0-9]+]]:_(s32) = G_CONSTANT i32 53
   ; CHECK:   [[C49:%[0-9]+]]:_(s32) = G_CONSTANT i32 54
   ; CHECK:   [[C50:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
   ; CHECK:   [[C51:%[0-9]+]]:_(s32) = G_CONSTANT i32 4352
   ; CHECK:   [[C52:%[0-9]+]]:_(s32) = G_CONSTANT i32 4353
   ; CHECK:   [[C53:%[0-9]+]]:_(s32) = G_CONSTANT i32 4354
   ; CHECK:   [[C54:%[0-9]+]]:_(s32) = G_CONSTANT i32 4355
   ; CHECK:   [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global
-  ; CHECK:   [[C55:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C55]](s64)
-  ; CHECK:   [[C56:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-  ; CHECK:   [[C57:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-  ; CHECK:   [[C58:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
-  ; CHECK:   [[C59:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-  ; CHECK:   [[C60:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
-  ; CHECK:   [[C61:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
-  ; CHECK:   [[C62:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
-  ; CHECK:   [[C63:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-  ; CHECK:   [[C64:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
-  ; CHECK:   [[C65:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
-  ; CHECK:   [[C66:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
-  ; CHECK:   [[C67:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-  ; CHECK:   [[C68:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
-  ; CHECK:   [[C69:%[0-9]+]]:_(s64) = G_CONSTANT i64 14
-  ; CHECK:   [[C70:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
-  ; CHECK:   [[C71:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-  ; CHECK:   [[C72:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
-  ; CHECK:   [[C73:%[0-9]+]]:_(s64) = G_CONSTANT i64 18
-  ; CHECK:   [[C74:%[0-9]+]]:_(s64) = G_CONSTANT i64 19
-  ; CHECK:   [[C75:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
-  ; CHECK:   [[C76:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
-  ; CHECK:   [[C77:%[0-9]+]]:_(s64) = G_CONSTANT i64 22
-  ; CHECK:   [[C78:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
-  ; CHECK:   [[C79:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-  ; CHECK:   [[C80:%[0-9]+]]:_(s64) = G_CONSTANT i64 25
-  ; CHECK:   [[C81:%[0-9]+]]:_(s64) = G_CONSTANT i64 26
-  ; CHECK:   [[C82:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
-  ; CHECK:   [[C83:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
-  ; CHECK:   [[C84:%[0-9]+]]:_(s64) = G_CONSTANT i64 29
-  ; CHECK:   [[C85:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
-  ; CHECK:   [[C86:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
-  ; CHECK:   [[C87:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-  ; CHECK:   [[C88:%[0-9]+]]:_(s64) = G_CONSTANT i64 33
-  ; CHECK:   [[C89:%[0-9]+]]:_(s64) = G_CONSTANT i64 34
-  ; CHECK:   [[C90:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
-  ; CHECK:   [[C91:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
-  ; CHECK:   [[C92:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
-  ; CHECK:   [[C93:%[0-9]+]]:_(s64) = G_CONSTANT i64 38
-  ; CHECK:   [[C94:%[0-9]+]]:_(s64) = G_CONSTANT i64 39
-  ; CHECK:   [[C95:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
-  ; CHECK:   [[C96:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
-  ; CHECK:   [[C97:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
-  ; CHECK:   [[C98:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
-  ; CHECK:   [[C99:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
-  ; CHECK:   [[C100:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
-  ; CHECK:   [[C101:%[0-9]+]]:_(s64) = G_CONSTANT i64 46
-  ; CHECK:   [[C102:%[0-9]+]]:_(s64) = G_CONSTANT i64 47
-  ; CHECK:   [[C103:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-  ; CHECK:   [[C104:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
-  ; CHECK:   [[C105:%[0-9]+]]:_(s64) = G_CONSTANT i64 50
-  ; CHECK:   [[C106:%[0-9]+]]:_(s64) = G_CONSTANT i64 51
-  ; CHECK:   [[C107:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
-  ; CHECK:   [[C108:%[0-9]+]]:_(s64) = G_CONSTANT i64 53
-  ; CHECK:   [[C109:%[0-9]+]]:_(s64) = G_CONSTANT i64 54
+  ; CHECK:   [[C55:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+  ; CHECK:   [[C56:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; CHECK:   [[C57:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+  ; CHECK:   [[C58:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+  ; CHECK:   [[C59:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+  ; CHECK:   [[C60:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+  ; CHECK:   [[C61:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+  ; CHECK:   [[C62:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
+  ; CHECK:   [[C63:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+  ; CHECK:   [[C64:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+  ; CHECK:   [[C65:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
+  ; CHECK:   [[C66:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
+  ; CHECK:   [[C67:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
+  ; CHECK:   [[C68:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+  ; CHECK:   [[C69:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
+  ; CHECK:   [[C70:%[0-9]+]]:_(s64) = G_CONSTANT i64 14
+  ; CHECK:   [[C71:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+  ; CHECK:   [[C72:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+  ; CHECK:   [[C73:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
+  ; CHECK:   [[C74:%[0-9]+]]:_(s64) = G_CONSTANT i64 18
+  ; CHECK:   [[C75:%[0-9]+]]:_(s64) = G_CONSTANT i64 19
+  ; CHECK:   [[C76:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
+  ; CHECK:   [[C77:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
+  ; CHECK:   [[C78:%[0-9]+]]:_(s64) = G_CONSTANT i64 22
+  ; CHECK:   [[C79:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
+  ; CHECK:   [[C80:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+  ; CHECK:   [[C81:%[0-9]+]]:_(s64) = G_CONSTANT i64 25
+  ; CHECK:   [[C82:%[0-9]+]]:_(s64) = G_CONSTANT i64 26
+  ; CHECK:   [[C83:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
+  ; CHECK:   [[C84:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
+  ; CHECK:   [[C85:%[0-9]+]]:_(s64) = G_CONSTANT i64 29
+  ; CHECK:   [[C86:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
+  ; CHECK:   [[C87:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
+  ; CHECK:   [[C88:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+  ; CHECK:   [[C89:%[0-9]+]]:_(s64) = G_CONSTANT i64 33
+  ; CHECK:   [[C90:%[0-9]+]]:_(s64) = G_CONSTANT i64 34
+  ; CHECK:   [[C91:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
+  ; CHECK:   [[C92:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
+  ; CHECK:   [[C93:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+  ; CHECK:   [[C94:%[0-9]+]]:_(s64) = G_CONSTANT i64 38
+  ; CHECK:   [[C95:%[0-9]+]]:_(s64) = G_CONSTANT i64 39
+  ; CHECK:   [[C96:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+  ; CHECK:   [[C97:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
+  ; CHECK:   [[C98:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+  ; CHECK:   [[C99:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
+  ; CHECK:   [[C100:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
+  ; CHECK:   [[C101:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
+  ; CHECK:   [[C102:%[0-9]+]]:_(s64) = G_CONSTANT i64 46
+  ; CHECK:   [[C103:%[0-9]+]]:_(s64) = G_CONSTANT i64 47
+  ; CHECK:   [[C104:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+  ; CHECK:   [[C105:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
+  ; CHECK:   [[C106:%[0-9]+]]:_(s64) = G_CONSTANT i64 50
+  ; CHECK:   [[C107:%[0-9]+]]:_(s64) = G_CONSTANT i64 51
+  ; CHECK:   [[C108:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
+  ; CHECK:   [[C109:%[0-9]+]]:_(s64) = G_CONSTANT i64 53
+  ; CHECK:   [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 54
   ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.tmp
   ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
   ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.56
   ; CHECK:   G_BR %bb.61
   ; CHECK: bb.61.bb:
   ; CHECK:   successors: %bb.2(0x40000000), %bb.62(0x40000000)
   ; CHECK:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
   ; CHECK:   G_BRCOND [[ICMP1]](s1), %bb.2
define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
   ; CHECK:   G_BR %bb.56
   ; CHECK: bb.54.bb55:
   ; CHECK:   successors: %bb.56(0x80000000)
   ; CHECK:   G_BR %bb.56
   ; CHECK: bb.55.bb56:
   ; CHECK:   successors: %bb.56(0x80000000)
   ; CHECK: bb.56.bb57:
   ; CHECK:   successors: %bb.59(0x80000000)
-  ; CHECK:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C55]](s64), %bb.1, [[C56]](s64), %bb.2, [[C57]](s64), %bb.3, [[C58]](s64), %bb.4, [[C59]](s64), %bb.5, [[C60]](s64), %bb.6, [[C61]](s64), %bb.7, [[C62]](s64), %bb.8, [[C63]](s64), %bb.9, [[C64]](s64), %bb.10, [[C65]](s64), %bb.11, [[C66]](s64), %bb.12, [[C67]](s64), %bb.13, [[C68]](s64), %bb.14, [[C69]](s64), %bb.15, [[C70]](s64), %bb.16, [[C71]](s64), %bb.17, [[C72]](s64), %bb.18, [[C73]](s64), %bb.19, [[C74]](s64), %bb.20, [[C75]](s64), %bb.21, [[C76]](s64), %bb.22, [[C77]](s64), %bb.23, [[C78]](s64), %bb.24, [[C79]](s64), %bb.25, [[C80]](s64), %bb.26, [[C81]](s64), %bb.27, [[C82]](s64), %bb.28, [[C83]](s64), %bb.29, [[C84]](s64), %bb.30, [[C85]](s64), %bb.31, [[C86]](s64), %bb.32, [[C87]](s64), %bb.33, [[C88]](s64), %bb.34, [[C89]](s64), %bb.35, [[C90]](s64), %bb.36, [[C91]](s64), %bb.37, [[C92]](s64), %bb.38, [[C93]](s64), %bb.39, [[C94]](s64), %bb.40, [[C95]](s64), %bb.41, [[C96]](s64), %bb.42, [[C97]](s64), %bb.43, [[C98]](s64), %bb.44, [[C99]](s64), %bb.45, [[C100]](s64), %bb.46, [[C101]](s64), %bb.47, [[C102]](s64), %bb.48, [[C103]](s64), %bb.49, [[C104]](s64), %bb.50, [[C105]](s64), %bb.51, [[C106]](s64), %bb.52, [[C107]](s64), %bb.53, [[C108]](s64), %bb.54, [[C109]](s64), %bb.55
-  ; CHECK:   [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-  ; CHECK:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[PHI]], [[C110]]
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C56]](s64), %bb.1, [[C57]](s64), %bb.2, [[C58]](s64), %bb.3, [[C59]](s64), %bb.4, [[C60]](s64), %bb.5, [[C61]](s64), %bb.6, [[C62]](s64), %bb.7, [[C63]](s64), %bb.8, [[C64]](s64), %bb.9, [[C65]](s64), %bb.10, [[C66]](s64), %bb.11, [[C67]](s64), %bb.12, [[C68]](s64), %bb.13, [[C69]](s64), %bb.14, [[C70]](s64), %bb.15, [[C71]](s64), %bb.16, [[C72]](s64), %bb.17, [[C73]](s64), %bb.18, [[C74]](s64), %bb.19, [[C75]](s64), %bb.20, [[C76]](s64), %bb.21, [[C77]](s64), %bb.22, [[C78]](s64), %bb.23, [[C79]](s64), %bb.24, [[C80]](s64), %bb.25, [[C81]](s64), %bb.26, [[C82]](s64), %bb.27, [[C83]](s64), %bb.28, [[C84]](s64), %bb.29, [[C85]](s64), %bb.30, [[C86]](s64), %bb.31, [[C87]](s64), %bb.32, [[C88]](s64), %bb.33, [[C89]](s64), %bb.34, [[C90]](s64), %bb.35, [[C91]](s64), %bb.36, [[C92]](s64), %bb.37, [[C93]](s64), %bb.38, [[C94]](s64), %bb.39, [[C95]](s64), %bb.40, [[C96]](s64), %bb.41, [[C97]](s64), %bb.42, [[C98]](s64), %bb.43, [[C99]](s64), %bb.44, [[C100]](s64), %bb.45, [[C101]](s64), %bb.46, [[C102]](s64), %bb.47, [[C103]](s64), %bb.48, [[C104]](s64), %bb.49, [[C105]](s64), %bb.50, [[C106]](s64), %bb.51, [[C107]](s64), %bb.52, [[C108]](s64), %bb.53, [[C109]](s64), %bb.54, [[C110]](s64), %bb.55
+  ; CHECK:   [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+  ; CHECK:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[PHI]], [[C111]]
   ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64)
-  ; CHECK:   [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-  ; CHECK:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C111]](s64)
+  ; CHECK:   [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+  ; CHECK:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C112]](s64)
   ; CHECK:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load 8 from %ir.tmp59)
   ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK:   $x0 = COPY [[COPY]](p0)
   ; CHECK:   $x1 = COPY [[LOAD]](p0)
   ; CHECK:   BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
   ; CHECK:   [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK:   G_BR %bb.59
define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
   ; CHECK:   $x1 = COPY [[COPY5]](p0)
   ; CHECK:   BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
   ; CHECK:   [[COPY6:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK: bb.59.bb68:
   ; CHECK:   RET_ReallyLR
   ; CHECK: bb.60.bb69:
   ; CHECK:   successors: %bb.58(0x40000000), %bb.57(0x40000000)
-  ; CHECK:   [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[INTTOPTR]]
+  ; CHECK:   [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
   ; CHECK:   G_BRCOND [[ICMP55]](s1), %bb.58
   ; CHECK:   G_BR %bb.57
 bb:
   %tmp = alloca [16 x i32], align 4
   switch i32 %arg1, label %bb69 [
     i32 3, label %bb57
     i32 4, label %bb3
     i32 6, label %bb4

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK-NEXT: $w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit $w0
 define i32 @test_urem(i32 %arg1, i32 %arg2) {
   %res = urem i32 %arg1, %arg2
   ret i32 %res
 }
 
 ; CHECK-LABEL: name: test_constant_null
-; CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZERO]]
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: $x0 = COPY [[NULL]]
 define i8* @test_constant_null() {
   ret i8* null
 }
 
 ; CHECK-LABEL: name: test_struct_memops
 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
 ; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4)

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll

 
 ; Verify that we can tail call musttail callees.
 declare void @must_callee(i8*)
 define void @foo(i32*) {
   ; COMMON-LABEL: name: foo
   ; COMMON: bb.1 (%ir-block.1):
   ; COMMON:   liveins: $x0
   ; COMMON:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-  ; COMMON:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-  ; COMMON:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
-  ; COMMON:   $x0 = COPY [[INTTOPTR]](p0)
+  ; COMMON:   [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+  ; COMMON:   $x0 = COPY [[C]](p0)
   ; COMMON:   TCRETURNdi @must_callee, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0
   musttail call void @must_callee(i8* null)
   ret void
 }

llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll

define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
   %sum = add i64 %lhs, %rhs
   store i64 %sum, i64* %addr
   ret void
 }
 
 ; CHECK-LABEL: name: test_call_stack
 ; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZERO]]
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
 ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](s64)
 ; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 1)
 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
 ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](s64)

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll

broken:
   ret void
 
 continue:
   ret void
 }
 
 ; CHECK-LABEL: name: test_invoke_varargs
 
-; CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZERO]]
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
 
 ; CHECK: $x0 = COPY [[NULL]]
 
 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
 ; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
 ; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFFSET]](s64)

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll

 ; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -o - %s | FileCheck %s
 
 target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 
 define void @snork() {
 bb:
   %tmp1 = getelementptr i16, i16* null, i64 0
   %tmp5 = getelementptr i16, i16* null, i64 2
   %tmp6 = load i16, i16* %tmp1, align 2, !tbaa !0
   store i16 %tmp6, i16* %tmp5, align 2, !tbaa !0
-  ; CHECK: %5:_(s16) = G_LOAD %2(p0) :: (load 2 from %ir.tmp1, !tbaa !0)
-  ; CHECK: G_STORE %5(s16), %4(p0) :: (store 2 into %ir.tmp5, !tbaa !0)
+  ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD %{{[0-9]+}}(p0) :: (load 2 from %ir.tmp1, !tbaa !0)
+  ; CHECK: G_STORE [[LOAD]](s16), %{{[0-9]+}}(p0) :: (store 2 into %ir.tmp5, !tbaa !0)
   ret void
 }
 
 !0 = !{!1, !1, i64 0}
 !1 = !{!"short", !2, i64 0}
 !2 = !{!"omnipotent char", !3, i64 0}
 !3 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define i8 @const_s8() { ret i8 42 }
   define i16 @const_s16() { ret i16 42 }
   define i32 @const_s32() { ret i32 42 }
   define i64 @const_s64() { ret i64 1234567890123 }
+  define i8* @const_p0_0() { ret i8* null }
 
   define i32 @fconst_s32() { ret i32 42 }
   define i64 @fconst_s64() { ret i64 1234567890123 }
   define float @fconst_s32_0() { ret float 0.0 }
   define double @fconst_s64_0() { ret double 0.0 }
 
   define void @optnone_i64() optnone noinline { ret void }
   define void @opt_i64() { ret void }
bb.0:
     ; CHECK-LABEL: name: const_s64
     ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
     ; CHECK: $x0 = COPY [[MOVi64imm]]
     %0(s64) = G_CONSTANT i64 1234567890123
     $x0 = COPY %0(s64)
 ...
 
 ---
+name:            const_p0_0
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: const_p0_0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $xzr
+    ; CHECK: $x0 = COPY [[COPY]]
+    %0:gpr(p0) = G_CONSTANT i64 0
+    $x0 = COPY %0
+...
+
+---
 name:            fconst_s32
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: fpr }
 
 body:             |
   bb.0:

llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
 
 %type = type [4 x {i8, i32}]
 
 define i8*  @translate_element_size1(i64 %arg) {
   ; CHECK-LABEL: name: translate_element_size1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
-  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
-  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[COPY]](s64)
+  ; CHECK:   [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](s64)
   ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
   ; CHECK:   $x0 = COPY [[COPY1]](p0)
   ; CHECK:   RET_ReallyLR implicit $x0
   %tmp = getelementptr i8, i8* null, i64 %arg
   ret i8* %tmp
 }
 
 define %type* @first_offset_const(%type* %addr) {