[ARM,CDE] Cosmetic changes, additonal driver tests

[miyuki]

Summary

This is a follow-up patch addressing post-commit comments in
https://reviews.llvm.org/D74044:

• Add more Clang driver tests (-march=armv8.1m.main and -march=armv8.1m.main+mve.fp)
• Clang-format a chunk in ARMAsmParser.cpp
• Add a missing copyright header to ARMInstrCDE.td

[SjoerdMeijer]

Cheers, LGTM

clang/test/Driver/arm-cde.c

-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-NOCDE
-// CHECK-NOCDE: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V81
+// CHECK-NOCDE-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-NOCDE-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp0"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp1"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp2"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp3"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp4"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp5"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp6"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp7"
 
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE1
-// CHECK-CDE1: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+mve.fp+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81MVE
+// CHECK-CDE1-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE1-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE-DAG: "-target-feature" "+mve.fp"
 // CHECK-CDE1-DAG: "-target-feature" "+cdecp0"
 // CHECK-CDE1-DAG: "-target-feature" "+cdecp3"
 
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE2
-// CHECK-CDE2: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V81
+// CHECK-CDE2-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE2-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp1"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp2"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp4"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp5"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp6"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp7"

llvm/lib/Target/ARM/ARMInstrCDE.td

+//===-- ARMInstrCDE.td - CDE support for ARM ---------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Arm CDE (Custom Datapath Extension) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
 // Immediate operand of arbitrary bit width
 class BitWidthImmOperand<int width>
   : ImmAsmOperand<0, !add(!shl(1, width), -1)> {
   let Name = "Imm"#width#"b";
 }
 
 class BitWidthImm<int width>
   : Operand<i32>,

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::t2SMULL: {
     unsigned RdLo = Inst.getOperand(1).getReg();
     if(RdHi == RdLo) {
       return Error(Loc,
                    "unpredictable instruction, RdHi and RdLo must be different");
     }
     break;
   }
 
-  case ARM::CDE_CX1: case ARM::CDE_CX1A: case ARM::CDE_CX1D: case ARM::CDE_CX1DA:
-  case ARM::CDE_CX2: case ARM::CDE_CX2A: case ARM::CDE_CX2D: case ARM::CDE_CX2DA:
-  case ARM::CDE_CX3: case ARM::CDE_CX3A: case ARM::CDE_CX3D: case ARM::CDE_CX3DA:
-  case ARM::CDE_VCX1_vec:  case ARM::CDE_VCX1_fpsp:  case ARM::CDE_VCX1_fpdp:
-  case ARM::CDE_VCX1A_vec: case ARM::CDE_VCX1A_fpsp: case ARM::CDE_VCX1A_fpdp:
-  case ARM::CDE_VCX2_vec:  case ARM::CDE_VCX2_fpsp:  case ARM::CDE_VCX2_fpdp:
-  case ARM::CDE_VCX2A_vec: case ARM::CDE_VCX2A_fpsp: case ARM::CDE_VCX2A_fpdp:
-  case ARM::CDE_VCX3_vec:  case ARM::CDE_VCX3_fpsp:  case ARM::CDE_VCX3_fpdp:
-  case ARM::CDE_VCX3A_vec: case ARM::CDE_VCX3A_fpsp: case ARM::CDE_VCX3A_fpdp: {
+  case ARM::CDE_CX1:
+  case ARM::CDE_CX1A:
+  case ARM::CDE_CX1D:
+  case ARM::CDE_CX1DA:
+  case ARM::CDE_CX2:
+  case ARM::CDE_CX2A:
+  case ARM::CDE_CX2D:
+  case ARM::CDE_CX2DA:
+  case ARM::CDE_CX3:
+  case ARM::CDE_CX3A:
+  case ARM::CDE_CX3D:
+  case ARM::CDE_CX3DA:
+  case ARM::CDE_VCX1_vec:
+  case ARM::CDE_VCX1_fpsp:
+  case ARM::CDE_VCX1_fpdp:
+  case ARM::CDE_VCX1A_vec:
+  case ARM::CDE_VCX1A_fpsp:
+  case ARM::CDE_VCX1A_fpdp:
+  case ARM::CDE_VCX2_vec:
+  case ARM::CDE_VCX2_fpsp:
+  case ARM::CDE_VCX2_fpdp:
+  case ARM::CDE_VCX2A_vec:
+  case ARM::CDE_VCX2A_fpsp:
+  case ARM::CDE_VCX2A_fpdp:
+  case ARM::CDE_VCX3_vec:
+  case ARM::CDE_VCX3_fpsp:
+  case ARM::CDE_VCX3_fpdp:
+  case ARM::CDE_VCX3A_vec:
+  case ARM::CDE_VCX3A_fpsp:
+  case ARM::CDE_VCX3A_fpdp: {
     assert(Inst.getOperand(1).isImm() &&
            "CDE operand 1 must be a coprocessor ID");
     int64_t Coproc = Inst.getOperand(1).getImm();
     if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI))
       return Error(Operands[1]->getStartLoc(),
                    "coprocessor must be configured as CDE");
     else if (Coproc >= 8)
       return Error(Operands[1]->getStartLoc(),
                    "coprocessor must be in the range [p0, p7]");
     break;
   }
 
-  case ARM::t2CDP: case ARM::t2CDP2:
-  case ARM::t2LDC2L_OFFSET: case ARM::t2LDC2L_OPTION: case ARM::t2LDC2L_POST: case ARM::t2LDC2L_PRE:
-  case ARM::t2LDC2_OFFSET: case ARM::t2LDC2_OPTION: case ARM::t2LDC2_POST: case ARM::t2LDC2_PRE:
-  case ARM::t2LDCL_OFFSET: case ARM::t2LDCL_OPTION: case ARM::t2LDCL_POST: case ARM::t2LDCL_PRE:
-  case ARM::t2LDC_OFFSET: case ARM::t2LDC_OPTION: case ARM::t2LDC_POST: case ARM::t2LDC_PRE:
-  case ARM::t2MCR: case ARM::t2MCR2: case ARM::t2MCRR: case ARM::t2MCRR2:
-  case ARM::t2MRC: case ARM::t2MRC2: case ARM::t2MRRC: case ARM::t2MRRC2:
-  case ARM::t2STC2L_OFFSET: case ARM::t2STC2L_OPTION: case ARM::t2STC2L_POST: case ARM::t2STC2L_PRE:
-  case ARM::t2STC2_OFFSET: case ARM::t2STC2_OPTION: case ARM::t2STC2_POST: case ARM::t2STC2_PRE:
-  case ARM::t2STCL_OFFSET: case ARM::t2STCL_OPTION: case ARM::t2STCL_POST: case ARM::t2STCL_PRE:
-  case ARM::t2STC_OFFSET: case ARM::t2STC_OPTION: case ARM::t2STC_POST: case ARM::t2STC_PRE: {
+  case ARM::t2CDP:
+  case ARM::t2CDP2:
+  case ARM::t2LDC2L_OFFSET:
+  case ARM::t2LDC2L_OPTION:
+  case ARM::t2LDC2L_POST:
+  case ARM::t2LDC2L_PRE:
+  case ARM::t2LDC2_OFFSET:
+  case ARM::t2LDC2_OPTION:
+  case ARM::t2LDC2_POST:
+  case ARM::t2LDC2_PRE:
+  case ARM::t2LDCL_OFFSET:
+  case ARM::t2LDCL_OPTION:
+  case ARM::t2LDCL_POST:
+  case ARM::t2LDCL_PRE:
+  case ARM::t2LDC_OFFSET:
+  case ARM::t2LDC_OPTION:
+  case ARM::t2LDC_POST:
+  case ARM::t2LDC_PRE:
+  case ARM::t2MCR:
+  case ARM::t2MCR2:
+  case ARM::t2MCRR:
+  case ARM::t2MCRR2:
+  case ARM::t2MRC:
+  case ARM::t2MRC2:
+  case ARM::t2MRRC:
+  case ARM::t2MRRC2:
+  case ARM::t2STC2L_OFFSET:
+  case ARM::t2STC2L_OPTION:
+  case ARM::t2STC2L_POST:
+  case ARM::t2STC2L_PRE:
+  case ARM::t2STC2_OFFSET:
+  case ARM::t2STC2_OPTION:
+  case ARM::t2STC2_POST:
+  case ARM::t2STC2_PRE:
+  case ARM::t2STCL_OFFSET:
+  case ARM::t2STCL_OPTION:
+  case ARM::t2STCL_POST:
+  case ARM::t2STCL_PRE:
+  case ARM::t2STC_OFFSET:
+  case ARM::t2STC_OPTION:
+  case ARM::t2STC_POST:
+  case ARM::t2STC_PRE: {
     unsigned Opcode = Inst.getOpcode();
     // Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags,
     // CopInd is the index of the coprocessor operand.
     size_t CopInd = 0;
     if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2)
       CopInd = 2;
     else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2)
       CopInd = 1;
-    assert(Inst.getOperand(CopInd).isImm() && "Operand must be a coprocessor ID");
+    assert(Inst.getOperand(CopInd).isImm() &&
+           "Operand must be a coprocessor ID");
     int64_t Coproc = Inst.getOperand(CopInd).getImm();
     // Operands[2] is the coprocessor operand at syntactic level
     if (ARM::isCDECoproc(Coproc, *STI))
-      return Error(Operands[2]->getStartLoc(), "coprocessor must be configured as GCP");
+      return Error(Operands[2]->getStartLoc(),
+                   "coprocessor must be configured as GCP");
     break;
   }
   }
 
   return false;
 }
 
 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {