[ARM] Fix infinite loop when lowering STRICT_FP_EXTEND

[john.brawn]

Summary

If the target has FP64 but not FP16 then we have custom lowering for FP_EXTEND and STRICT_FP_EXTEND with type f64. However if the extend is from f32 to f64 the current implementation will cause in infinite loop for STRICT_FP_EXTEND due to emitting a merge_values of the original node which after replacement becomes a merge_values of itself.

Fix this by not doing anything for f32 to f64 extend when we have FP64, though for STRICT_FP_EXTEND we have to do the strict-to-nonstrict mutation as that doesn't happen automatically for opcodes with custom lowering.

[SjoerdMeijer]

Perhaps I have missed it, but are the test that have been changed here actually doing any 32 -> 64 converts?

[john.brawn]

In D74559#1874435, @SjoerdMeijer wrote:

Perhaps I have missed it, but are the test that have been changed here actually doing any 32 -> 64 converts?

The test fpext_f32 tests 32 -> 64 converts. The test changes here are because we're now running the tests with ARMv7 (because ARMv7 by default doesn't have FP16 support), which doesn't have some instruction that we have in ARMv8.

[SjoerdMeijer]

Ah, thanks for clarifying. In that case, this looks like a straightforward fix to me: LGTM.

llvm/lib/Target/ARM/ARMISelLowering.cpp

          "Unexpected type for custom-lowering FP_EXTEND");
 
   assert((!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) &&
          "With both FP DP and 16, any FP conversion is legal!");
 
   assert(!(DstSz == 32 && Subtarget->hasFP16()) &&
          "With FP16, 16 to 32 conversion is legal!");
 
+  // Converting from 32 -> 64 is valid if we have FP64.
+  if (SrcSz == 32 && DstSz == 64 && Subtarget->hasFP64()) {
+    // FIXME: Remove this when we have strict fp instruction selection patterns
+    if (IsStrict) {
+      DAG.mutateStrictFPToFP(Op.getNode());
+    }
+    return Op;
+  }
+
   // Either we are converting from 16 -> 64, without FP16 and/or
   // FP.double-precision or without Armv8-fp. So we must do it in two
   // steps.
   // Or we are converting from 32 -> 64 without fp.double-precision or 16 -> 32
   // without FP16. So we must do a function call.
   SDLoc Loc(Op);
   RTLIB::Libcall LC;
   MakeLibCallOptions CallOptions;

llvm/test/CodeGen/ARM/fp-intrinsics.ll

-; RUN: llc -mtriple=armv8a-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP
+; RUN: llc -mtriple=armv8a-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP,CHECK-SP-V8,CHECK-DP-V8
 ; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOSP,CHECK-NODP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - -mattr=fp-armv8 | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - -mattr=fp-armv8sp | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-NODP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - -mattr=fp-armv8 | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP,CHECK-SP-V8,CHECK-DP-V8
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - -mattr=fp-armv8sp | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-NODP,CHECK-SP-V8
+; RUN: llc -mtriple=armv7a-none-eabi %s -o - -mattr=vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP,CHECK-SP-NOV8,CHECK-DP-NOV8
+; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOSP,CHECK-NODP
+; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - -mattr=vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-DP,CHECK-SP-NOV8,CHECK-DP-NOV8
+; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - -mattr=vfp4sp | FileCheck %s --check-prefixes=CHECK,CHECK-SP,CHECK-NODP,CHECK-SP-NOV8
 
 ; Check that constrained fp intrinsics are correctly lowered. In particular
 ; check that the valid combinations of single-precision and double-precision
 ; hardware being present or absent work as expected (i.e. we get an instruction
 ; when one is available, otherwise a libcall).
 
 ; FIXME: We're not generating the right instructions for some of these
 ; operations (see further FIXMEs down below).

 ; CHECK: bl exp2f
 define float @exp2_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.exp2.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: rint_f32:
 ; CHECK-NOSP: bl rintf
-; CHECK-SP: vrintx.f32
+; CHECK-SP-NOV8: bl rintf
+; CHECK-SP-V8: vrintx.f32
 define float @rint_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.rint.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: nearbyint_f32:
 ; CHECK-NOSP: bl nearbyintf
-; CHECK-SP: vrintr.f32
+; CHECK-SP-NOV8: bl nearbyintf
+; CHECK-SP-V8: vrintr.f32
 define float @nearbyint_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.nearbyint.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: lrint_f32:
 ; CHECK: bl lrintf
 define i32 @lrint_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.lrint.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: llrint_f32:
 ; CHECK: bl llrintf
 define i32 @llrint_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.llrint.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: maxnum_f32:
 ; CHECK-NOSP: bl fmaxf
-; CHECK-SP: vmaxnm.f32
+; CHECK-SP-NOV8: bl fmaxf
+; CHECK-SP-V8: vmaxnm.f32
 define float @maxnum_f32(float %x, float %y) #0 {
   %val = call float @llvm.experimental.constrained.maxnum.f32(float %x, float %y, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: minnum_f32:
 ; CHECK-NOSP: bl fminf
-; CHECK-SP: vminnm.f32
+; CHECK-SP-NOV8: bl fminf
+; CHECK-SP-V8: vminnm.f32
 define float @minnum_f32(float %x, float %y) #0 {
   %val = call float @llvm.experimental.constrained.minnum.f32(float %x, float %y, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: ceil_f32:
 ; CHECK-NOSP: bl ceilf
-; CHECK-SP: vrintp.f32
+; CHECK-SP-NOV8: bl ceilf
+; CHECK-SP-V8: vrintp.f32
 define float @ceil_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.ceil.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: floor_f32:
 ; CHECK-NOSP: bl floorf
-; CHECK-SP: vrintm.f32
+; CHECK-SP-NOV8: bl floorf
+; CHECK-SP-V8: vrintm.f32
 define float @floor_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.floor.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: lround_f32:
 ; CHECK: bl lroundf
 define i32 @lround_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.lround.f32(float %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: llround_f32:
 ; CHECK: bl llroundf
 define i32 @llround_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.llround.f32(float %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: round_f32:
 ; CHECK-NOSP: bl roundf
-; CHECK-SP: vrinta.f32
+; CHECK-SP-NOV8: bl roundf
+; CHECK-SP-V8: vrinta.f32
 define float @round_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.round.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: trunc_f32:
 ; CHECK-NOSP: bl truncf
-; CHECK-SP: vrintz.f32
+; CHECK-SP-NOV8: bl truncf
+; CHECK-SP-V8: vrintz.f32
 define float @trunc_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.trunc.f32(float %x, metadata !"fpexcept.strict") #0
   ret float %val
 }
 
 ; CHECK-LABEL: fcmp_olt_f32:
 ; CHECK-NOSP: bl __aeabi_fcmplt
 ; CHECK-SP: vcmp.f32

 ; CHECK: bl exp2
 define double @exp2_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.exp2.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: rint_f64:
 ; CHECK-NODP: bl rint
-; CHECK-DP: vrintx.f64
+; CHECK-DP-NOV8: bl rint
+; CHECK-DP-V8: vrintx.f64
 define double @rint_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.rint.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: nearbyint_f64:
 ; CHECK-NODP: bl nearbyint
-; CHECK-DP: vrintr.f64
+; CHECK-DP-NOV8: bl nearbyint
+; CHECK-DP-V8: vrintr.f64
 define double @nearbyint_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.nearbyint.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: lrint_f64:
 ; CHECK: bl lrint
 define i32 @lrint_f64(double %x) #0 {
   %val = call i32 @llvm.experimental.constrained.lrint.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: llrint_f64:
 ; CHECK: bl llrint
 define i32 @llrint_f64(double %x) #0 {
   %val = call i32 @llvm.experimental.constrained.llrint.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: maxnum_f64:
 ; CHECK-NODP: bl fmax
-; CHECK-DP: vmaxnm.f64
+; CHECK-DP-NOV8: bl fmax
+; CHECK-DP-V8: vmaxnm.f64
 define double @maxnum_f64(double %x, double %y) #0 {
   %val = call double @llvm.experimental.constrained.maxnum.f64(double %x, double %y, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: minnum_f64:
 ; CHECK-NODP: bl fmin
-; CHECK-DP: vminnm.f64
+; CHECK-DP-NOV8: bl fmin
+; CHECK-DP-V8: vminnm.f64
 define double @minnum_f64(double %x, double %y) #0 {
   %val = call double @llvm.experimental.constrained.minnum.f64(double %x, double %y, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: ceil_f64:
 ; CHECK-NODP: bl ceil
-; CHECK-DP: vrintp.f64
+; CHECK-DP-NOV8: bl ceil
+; CHECK-DP-V8: vrintp.f64
 define double @ceil_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.ceil.f64(double %x, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: floor_f64:
 ; CHECK-NODP: bl floor
-; CHECK-DP: vrintm.f64
+; CHECK-DP-NOV8: bl floor
+; CHECK-DP-V8: vrintm.f64
 define double @floor_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.floor.f64(double %x, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: lround_f64:
 ; CHECK: bl lround
 define i32 @lround_f64(double %x) #0 {
   %val = call i32 @llvm.experimental.constrained.lround.f64(double %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: llround_f64:
 ; CHECK: bl llround
 define i32 @llround_f64(double %x) #0 {
   %val = call i32 @llvm.experimental.constrained.llround.f64(double %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
 ; CHECK-LABEL: round_f64:
 ; CHECK-NODP: bl round
-; CHECK-DP: vrinta.f64
+; CHECK-DP-NOV8: bl round
+; CHECK-DP-V8: vrinta.f64
 define double @round_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.round.f64(double %x, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: trunc_f64:
 ; CHECK-NODP: bl trunc
-; CHECK-DP: vrintz.f64
+; CHECK-DP-NOV8: bl trunc
+; CHECK-DP-V8: vrintz.f64
 define double @trunc_f64(double %x) #0 {
   %val = call double @llvm.experimental.constrained.trunc.f64(double %x, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
 ; CHECK-LABEL: fcmp_olt_f64:
 ; CHECK-NODP: bl __aeabi_dcmplt
 ; CHECK-DP: vcmp.f64