[mlir][DeclarativeParser] Move several missed parsers over to the declarative form.

[rriddle]

Summary

Depends On D74276

[antiagainst]

Nice, thanks!

mlir/include/mlir/Dialect/LoopOps/LoopOps.td

let description = [{
     operand of "loop.reduce". Example for the custom format:
 
     ```mlir
       loop.reduce.return %res : f32
     ```
   }];
 
   let arguments = (ins AnyType:$result);
+  let assemblyFormat = "$result attr-dict `:` type($result)";
 }
 
 def TerminatorOp : Loop_Op<"terminator", [Terminator]> {
   let summary = "cf terminator operation";
   let description = [{
     "loop.terminator" is a special terminator operation for blocks inside
     loops. It terminates the region. This operation does _not_ have a custom
     syntax. However, `std` control operations omit the terminator in their

mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td

 
 class SPV_BitBinaryOp<string mnemonic, list<OpTrait> traits = []> :
       // All the operands type used in bit instructions are SPV_Integer.
       SPV_BinaryOp<mnemonic, SPV_Integer, SPV_Integer,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultType])>;
 
 class SPV_BitFieldExtractOp<string mnemonic, list<OpTrait> traits = []> :
-      SPV_Op<mnemonic, !listconcat(traits, [NoSideEffect])> {
+      SPV_Op<mnemonic, !listconcat(traits,
+             [NoSideEffect, AllTypesMatch<["base", "result"]>])> {
   let arguments = (ins
     SPV_ScalarOrVectorOf<SPV_Integer>:$base,
     SPV_Integer:$offset,
     SPV_Integer:$count
   );
 
   let results = (outs
     SPV_ScalarOrVectorOf<SPV_Integer>:$result
   );
 
-  let parser = [{ return ::parseBitFieldExtractOp(parser, result); }];
-  let printer = [{ ::printBitFieldExtractOp(this->getOperation(), p); }];
-  let verifier = [{ return ::verifyBitFieldExtractOp(this->getOperation()); }];
+  let verifier = [{ return success(); }];
+
+  let assemblyFormat = [{
+    operands attr-dict `:` type($base) `,` type($offset) `,` type($count)
+  }];
 }
 
 class SPV_BitUnaryOp<string mnemonic, list<OpTrait> traits = []> :
       SPV_UnaryOp<mnemonic, SPV_Integer, SPV_Integer,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultType])>;
 
 class SPV_ShiftOp<string mnemonic, list<OpTrait> traits = []> :

mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td

let description = [{
     `spv.loop` op. This op does not have a corresponding instruction in the
     SPIR-V binary format; it's solely for structural purpose.
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
-  let parser = [{ return parseNoIOOp(parser, result); }];
-  let printer = [{ printNoIOOp(getOperation(), p); }];
+  let assemblyFormat = "attr-dict";
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 
 // -----
 
let description = [{
     return-op ::= `spv.Return`
     ```
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
-  let parser = [{ return parseNoIOOp(parser, result); }];
-  let printer = [{ printNoIOOp(getOperation(), p); }];
+  let assemblyFormat = "attr-dict";
 }
 
 // -----
 
 def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> {
   let summary = "Declares that this block is not reachable in the CFG.";
 
   let description = [{
     This instruction must be the last instruction in a block.
 
     ### Custom assembly form
 
     ```
     unreachable-op ::= `spv.Unreachable`
     ```
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
-  let parser = [{ return parseNoIOOp(parser, result); }];
-  let printer = [{ printNoIOOp(getOperation(), p); }];
+  let assemblyFormat = "attr-dict";
 }
 
 // -----
 
 def SPV_ReturnValueOp : SPV_Op<"ReturnValue", [InFunctionScope, Terminator]> {
   let summary = "Return a value from a function.";
 
   let description = [{

mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td

let description = [{
     not be serialized into the binary format; it is used solely to satisfy
     the structual requirement that an block must be ended with a terminator.
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
-  let parser = [{ return parseNoIOOp(parser, result); }];
-  let printer = [{ printNoIOOp(getOperation(), p); }];
+  let assemblyFormat = "attr-dict";
 
   let verifier = [{ return success(); }];
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 

mlir/lib/Dialect/LoopOps/LoopOps.cpp

static LogicalResult verify(ReduceReturnOp op) {
   auto reduceOp = cast<ReduceOp>(op.getParentOp());
   Type reduceType = reduceOp.operand().getType();
   if (reduceType != op.result().getType())
     return op.emitOpError() << "needs to have type " << reduceType
                             << " (the type of the enclosing ReduceOp)";
   return success();
 }
 
-static ParseResult parseReduceReturnOp(OpAsmParser &parser,
-                                       OperationState &result) {
-  OpAsmParser::OperandType operand;
-  Type resultType;
-  if (parser.parseOperand(operand) || parser.parseColonType(resultType) ||
-      parser.resolveOperand(operand, resultType, result.operands))
-    return failure();
-
-  return success();
-}
-
-static void print(OpAsmPrinter &p, ReduceReturnOp op) {
-  p << op.getOperationName() << " " << op.result() << " : "
-    << op.result().getType();
-}
-
 //===----------------------------------------------------------------------===//
 // TableGen'd op method definitions
 //===----------------------------------------------------------------------===//
 
 #define GET_OP_CLASSES
 #include "mlir/Dialect/LoopOps/LoopOps.cpp.inc"

mlir/lib/Dialect/SPIRV/SPIRVOps.cpp

 namespace {
 #include "SPIRVCanonicalization.inc"
 }
 
 //===----------------------------------------------------------------------===//
 // Common parsers and printers
 //===----------------------------------------------------------------------===//
 
-static ParseResult parseBitFieldExtractOp(OpAsmParser &parser,
-                                          OperationState &state) {
-  SmallVector<OpAsmParser::OperandType, 3> operandInfo;
-  Type baseType;
-  Type offsetType;
-  Type countType;
-  auto loc = parser.getCurrentLocation();
-
-  if (parser.parseOperandList(operandInfo, 3) || parser.parseColon() ||
-      parser.parseType(baseType) || parser.parseComma() ||
-      parser.parseType(offsetType) || parser.parseComma() ||
-      parser.parseType(countType) ||
-      parser.resolveOperands(operandInfo, {baseType, offsetType, countType},
-                             loc, state.operands)) {
-    return failure();
-  }
-  state.addTypes(baseType);
-  return success();
-}
-
-static void printBitFieldExtractOp(Operation *op, OpAsmPrinter &printer) {
-  printer << op->getName() << ' ' << op->getOperands() << " : "
-          << op->getOperandTypes();
-}
-
-static LogicalResult verifyBitFieldExtractOp(Operation *op) {
-  if (op->getOperand(0).getType() != op->getResult(0).getType()) {
-    return op->emitError("expected the same type for the first operand and "
-                         "result, but provided ")
-           << op->getOperand(0).getType() << " and "
-           << op->getResult(0).getType();
-  }
-  return success();
-}
-
 // Parses an atomic update op. If the update op does not take a value (like
 // AtomicIIncrement) `hasValue` must be false.
 static ParseResult parseAtomicUpdateOp(OpAsmParser &parser,
                                        OperationState &state, bool hasValue) {
   spirv::Scope scope;
   spirv::MemorySemantics memoryScope;
   SmallVector<OpAsmParser::OperandType, 2> operandInfo;
   OpAsmParser::OperandType ptrInfo, valueInfo;
if (groupOp->getNumOperands() > 1) {
 
     if (!llvm::isPowerOf2_32(clusterSize))
       return groupOp->emitOpError(
           "cluster size operand must be a power of two");
   }
   return success();
 }
 
-// Parses an op that has no inputs and no outputs.
-static ParseResult parseNoIOOp(OpAsmParser &parser, OperationState &state) {
-  if (parser.parseOptionalAttrDict(state.attributes))
-    return failure();
-  return success();
-}
-
-// Prints an op that has no inputs and no outputs.
-static void printNoIOOp(Operation *op, OpAsmPrinter &printer) {
-  printer << op->getName();
-  printer.printOptionalAttrDict(op->getAttrs());
-}
-
 static ParseResult parseUnaryOp(OpAsmParser &parser, OperationState &state) {
   OpAsmParser::OperandType operandInfo;
   Type type;
   if (parser.parseOperand(operandInfo) || parser.parseColonType(type) ||
       parser.resolveOperands(operandInfo, type, state.operands)) {
     return failure();
   }
   state.addTypes(type);

mlir/test/Dialect/SPIRV/ops.mlir

func @bit_field_u_extract_vec(%base: vector<3xi32>, %offset: i8, %count: i8) -> vector<3xi32> {
   // CHECK: {{%.*}} = spv.BitFieldUExtract {{%.*}}, {{%.*}}, {{%.*}} : vector<3xi32>, i8, i8
   %0 = spv.BitFieldUExtract %base, %offset, %count : vector<3xi32>, i8, i8
   spv.ReturnValue %0 : vector<3xi32>
 }
 
 // -----
 
 func @bit_field_u_extract_invalid_result_type(%base: vector<3xi32>, %offset: i32, %count: i16) -> vector<4xi32> {
-  // expected-error @+1 {{expected the same type for the first operand and result, but provided 'vector<3xi32>' and 'vector<4xi32>'}}
+  // expected-error @+1 {{failed to verify that all of {base, result} have same type}}
   %0 = "spv.BitFieldUExtract" (%base, %offset, %count) : (vector<3xi32>, i32, i16) -> vector<4xi32>
   spv.ReturnValue %0 : vector<4xi32>
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.BitReverse