[AMDGPU] override isHighLatencyDef

[rampitec]

Summary

SIMachineScheduler uses isHighLatencyInstruction with the same
sematincs, but TargetInstrInfo has virtual isHighLatencyDef
method, so override it instead.

Added FLAT to the list of high latency opcodes and a check for
mayLoad since stores are not technically high latency in terms
of data dependency.

This change did not produce any visible impact on our tests.

[foad]

I have no objection to this patch, but I'm not sure isHighLatencyDef will ever be called by generic code. I think the latency information ususally comes from the sched model instead. Also note that TargetInstrInfo::defaultDefLatency never calls isHighLatencyDef on a load instruction!

[rampitec]

In D73582#1846426, @foad wrote:

I have no objection to this patch, but I'm not sure isHighLatencyDef will ever be called by generic code. I think the latency information ususally comes from the sched model instead. Also note that TargetInstrInfo::defaultDefLatency never calls isHighLatencyDef on a load instruction!

Yes, I think this is mostly NFC. It is just confusing to have a very similar method and do not override a generic one.

llvm/lib/Target/AMDGPU/SIInstrInfo.h

int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
     return MI.getOperand(Idx).getImm();
   }
 
   uint64_t getDefaultRsrcDataFormat() const;
   uint64_t getScratchRsrcWords23() const;
 
   bool isLowLatencyInstruction(const MachineInstr &MI) const;
-  bool isHighLatencyInstruction(const MachineInstr &MI) const;
+  bool isHighLatencyDef(int Opc) const override;
 
   /// Return the descriptor of the target-specific machine instruction
   /// that corresponds to the specified pseudo or native opcode.
   const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
     return get(pseudoToMCOpcode(Opcode));
   }
 
   unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 }
 
 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {
   unsigned Opc = MI.getOpcode();
 
   return isSMRD(Opc);
 }
 
-bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {
-  unsigned Opc = MI.getOpcode();
-
-  return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
+bool SIInstrInfo::isHighLatencyDef(int Opc) const {
+  return get(Opc).mayLoad() &&
+         (isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
 }
 
 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
                                     int &FrameIndex) const {
   const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
   if (!Addr || !Addr->isFI())
     return AMDGPU::NoRegister;
 

llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

for (unsigned i = 0, e = (unsigned)SUnits.size(); i != e; ++i) {
     SUnit *SU = &SUnits[i];
     const MachineOperand *BaseLatOp;
     int64_t OffLatReg;
     if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
       IsLowLatencySU[i] = 1;
       if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
                                          TRI))
         LowLatencyOffset[i] = OffLatReg;
-    } else if (SITII->isHighLatencyInstruction(*SU->getInstr()))
+    } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
       IsHighLatencySU[i] = 1;
   }
 
   SIScheduler Scheduler(this);
   Best = Scheduler.scheduleVariant(SISchedulerBlockCreatorVariant::LatenciesAlone,
                                    SISchedulerBlockSchedulerVariant::BlockLatencyRegUsage);
 
   // if VGPR usage is extremely high, try other good performing variants