[AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr

[foad]

Summary

This is in preparation for getMemOperandsWithOffset returning more base
operands.

[merge_guards_bot]

Unit tests: pass. 62206 tests passed, 0 failed and 815 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::getMemOperandsWithOffset(
 
   return false;
 }
 
 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
                                   const MachineOperand &BaseOp1,
                                   const MachineInstr &MI2,
                                   const MachineOperand &BaseOp2) {
-  // Support only base operands with base registers.
-  // Note: this could be extended to support FI operands.
-  if (!BaseOp1.isReg() || !BaseOp2.isReg())
-    return false;
-
   if (BaseOp1.isIdenticalTo(BaseOp2))
     return true;
 
   if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
     return false;
 
   auto MO1 = *MI1.memoperands_begin();
   auto MO2 = *MI2.memoperands_begin();