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Differential D72544

GlobalISel: Fix assertion on wide G_ZEXT sources
ClosedPublic

Authored by arsenm on Jan 10 2020, 2:55 PM.

Details

Reviewers
aemerson
paquette
aditya_nandakumar
dsanders
Petar.Avramovic
Summary

It's possible to have a type that needs a mask greater than 64-bits.

Diff Detail

Event Timeline

arsenm created this revision.Jan 10 2020, 2:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 10 2020, 2:55 PM
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Petar.Avramovic accepted this revision.Jan 13 2020, 2:39 AM

LGTM.

This revision is now accepted and ready to land.Jan 13 2020, 2:39 AM
arsenm closed this revision.Jan 13 2020, 5:30 AM

d7d88b9d8b3efd8b4b07074aa64b5b4136a35b2c

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
3 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
25 lines

Diff 237441

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines bool tryCombineZExt(MachineInstr &MI,
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
isConstantUnsupported(DstTy)) isConstantUnsupported(DstTy))
return false; return false;
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits()); APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue()); auto MIBMask = Builder.buildConstant(
DstTy, Mask.zext(DstTy.getScalarSizeInBits()));
Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
MIBMask); MIBMask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// Try to fold zext(g_constant) when the larger constant type is legal. // Try to fold zext(g_constant) when the larger constant type is legal.
// Can't use MIPattern because we don't have a specific constant in mind. // Can't use MIPattern because we don't have a specific constant in mind.
▲ Show 20 Lines • Show All 535 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT2]], [[COPY2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT2]], [[COPY2]]
; CHECK: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[AND1]](s32), 64 ; CHECK: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[AND1]](s32), 64
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0 %1:_(<3 x s16>) = G_TRUNC %0
%2:_(<3 x s32>) = G_ZEXT %1 %2:_(<3 x s32>) = G_ZEXT %1
$vgpr0_vgpr1_vgpr2 = COPY %2 $vgpr0_vgpr1_vgpr2 = COPY %2
... ...
# Test for "Too many bits for uint64_t" assertion when combining
# zexts with wide sources.
---
name: test_zext_128_trunc_s128_merge
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_128_trunc_s128_merge
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr0_vgpr1
%2:_(s128) = G_MERGE_VALUES %0, %1
%3:_(s96) = G_TRUNC %2
%4:_(s128) = G_ZEXT %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
...