[ARM] Use correct TRAP opcode for thumb in FastISel

[dmgreen]

Summary

We were previously unconditionally using the ARM::TRAP opcode, even under Thumb. My understanding is that these are essentially the same thing (they both result in a trap under Thumb), but the ARM::TRAP opcode is marked as requiring IsARM, so it is more correct to use ARM::tTRAP.

The only test here just updates a case of the wrong code being used. The idea is to attempt to enable PREDICATE_VERIFIER for the arm target, which will test this kind of thing more thoroughly. There are some mulv5 vs mul and global ISel problems to sort out first though.

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMFastISel.cpp

if (!MSI.getLength()->getType()->isIntegerTy(32))
       return false;
 
     if (MSI.getDestAddressSpace() > 255)
       return false;
 
     return SelectCall(&I, "memset");
   }
   case Intrinsic::trap: {
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
-      Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
+    unsigned Opcode;
+    if (Subtarget->isThumb())
+      Opcode = ARM::tTRAP;
+    else
+      Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode));
     return true;
   }
   }
 }
 
 bool ARMFastISel::SelectTrunc(const Instruction *I) {
   // The high bits for a type smaller than the register size are assumed to be
   // undefined.

llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir

body: |
   bb.1:
     liveins: $r2, $r4
     renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4)
     dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg
     renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4)
     renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
   bb.2:
     liveins: $r4
-    TRAP
+    tTRAP