[PowerPC] Change default for unaligned FP access for older subtargets

[nemanjai]

Summary

This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40554

Some CPU's trap to the kernel on unaligned floating point access and there are kernels that do not handle the interrupt. The program then fails with a SIGBUS according to the PR. This just switches the default for unaligned access to only allow it on recent server CPUs that are known to allow this.

[nemanjai]

Add the feature to the BG cores as well.

[hfinkel]

In D71954#1797765, @nemanjai wrote:

Add the feature to the BG cores as well.

BG did allow this, but IIRC, only some finite number of times (before it really slowed down by logging a lot from the kernel). Maybe this was just for the vector types, but regardless, I'd leave this off for the BG cores.

Otherwise, LGTM.

llvm/lib/Target/PowerPC/PPC.td

SubtargetFeature<"invariant-function-descriptors",
                    "HasInvariantFunctionDescriptors", "true",
                    "Assume function descriptors are invariant">;
 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
                                        "Always use indirect calls">;
 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
                                   "Enable Hardware Transactional Memory instructions">;
 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
                                         "Implement mftb using the mfspr instruction">;
+def FeatureUnalignedFloats :
+  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
+                   "true", "CPU does not trap on unaligned FP access">;
 def FeaturePPCPreRASched:
   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
                    "Use PowerPC pre-RA scheduling strategy">;
 def FeaturePPCPostRASched:
   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
                    "Use PowerPC post-RA scheduling strategy">;
 def FeatureFloat128 :
   SubtargetFeature<"float128", "HasFloat128", "true",
list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
                                                   FeatureCMPB,
                                                   FeatureLDBRX,
                                                   Feature64Bit,
                                                   /* Feature64BitRegs, */
                                                   FeatureBPERMD,
                                                   FeatureExtDiv,
                                                   FeatureMFTB,
                                                   DeprecatedDST,
-                                                  FeatureTwoConstNR];
+                                                  FeatureTwoConstNR,
+                                                  FeatureUnalignedFloats];
   list<SubtargetFeature> P7SpecificFeatures = [];
   list<SubtargetFeature> P7Features =
     !listconcat(P7InheritableFeatures, P7SpecificFeatures);
 
   // Power8
   list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8,
                                                  FeatureP8Altivec,
                                                  FeatureP8Vector,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
   // Although accessing unaligned addresses is not as efficient as accessing
   // aligned addresses, it is generally more efficient than manual expansion,
   // and generally only traps for software emulation when crossing page
   // boundaries.
 
   if (!VT.isSimple())
     return false;
 
+  if (VT.isFloatingPoint() && !Subtarget.allowsUnalignedFPAccess())
+    return false;
+
   if (VT.getSimpleVT().isVector()) {
     if (Subtarget.hasVSX()) {
       if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
           VT != MVT::v4f32 && VT != MVT::v4i32)
         return false;
     } else {
       return false;
     }

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool HasCMPB;
   bool HasLDBRX;
   bool IsBookE;
   bool HasOnlyMSYNC;
   bool IsE500;
   bool IsPPC4xx;
   bool IsPPC6xx;
   bool FeatureMFTB;
+  bool AllowsUnalignedFPAccess;
   bool DeprecatedDST;
   bool HasLazyResolverStubs;
   bool IsLittleEndian;
   bool HasICBT;
   bool HasInvariantFunctionDescriptors;
   bool HasPartwordAtomics;
   bool HasDirectMove;
   bool HasHTM;
public:
   bool isBookE() const { return IsBookE; }
   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
   bool isPPC4xx() const { return IsPPC4xx; }
   bool isPPC6xx() const { return IsPPC6xx; }
   bool isSecurePlt() const {return SecurePlt; }
   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
   bool isE500() const { return IsE500; }
   bool isFeatureMFTB() const { return FeatureMFTB; }
+  bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
   bool isDeprecatedDST() const { return DeprecatedDST; }
   bool hasICBT() const { return HasICBT; }
   bool hasInvariantFunctionDescriptors() const {
     return HasInvariantFunctionDescriptors;
   }
   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }

llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll

-; RUN: llc -verify-machineinstrs -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mattr=-vsx \
+; RUN:   -mattr=+allow-unaligned-fp-access < %s | FileCheck %s
 ; ModuleID = 'foo.c'
 
 target triple = "powerpc-unknown-linux-gnu"
 
   %struct.anon = type <{ i8, float }>
 @s = global %struct.anon <{ i8 3, float 0x4014666660000000 }>    ; <%struct.anon*> [#uses=1]
 @u = global <{ i8, double }> <{ i8 3, double 5.100000e+00 }>    ; <<{ i8, double }>*> [#uses=1]
 @t = weak global %struct.anon zeroinitializer   ; <%struct.anon*> [#uses=2]

llvm/test/CodeGen/PowerPC/unaligned-floats.ll

+; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -mtriple=powerpc-- \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mattr=allow-unaligned-fp-access -ppc-asm-full-reg-names \
+; RUN:   -mtriple=powerpc-- -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc-- \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefix=UNALIGN
+
+; Test case as provided by author in https://bugs.llvm.org/show_bug.cgi?id=40554
+%struct.anon = type { i32, [5 x i8] }
+
+@s = dso_local local_unnamed_addr global %struct.anon { i32 0, [5 x i8] c"\00B\F6\E9y" }, align 4
+@.str = private unnamed_addr constant [4 x i8] c"%g\0A\00", align 1
+; Function Attrs: nofree nounwind
+define dso_local i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:       lfs f1, 5(r3)
+; CHECK:       blr
+;
+; UNALIGN-LABEL: main:
+; UNALIGN:       lfs f1, 12(r1)
+; UNALIGN:       blr
+entry:
+  %0 = load i8, i8* getelementptr inbounds (%struct.anon, %struct.anon* @s, i32 0, i32 1, i32 1), align 1
+  %conv = zext i8 %0 to i32
+  %shl = shl nuw i32 %conv, 24
+  %1 = load i8, i8* getelementptr inbounds (%struct.anon, %struct.anon* @s, i32 0, i32 1, i32 2), align 2
+  %conv1 = zext i8 %1 to i32
+  %shl2 = shl nuw nsw i32 %conv1, 16
+  %add = or i32 %shl2, %shl
+  %2 = load i8, i8* getelementptr inbounds (%struct.anon, %struct.anon* @s, i32 0, i32 1, i32 3), align 1
+  %conv3 = zext i8 %2 to i32
+  %shl4 = shl nuw nsw i32 %conv3, 8
+  %add5 = or i32 %add, %shl4
+  %3 = load i8, i8* getelementptr inbounds (%struct.anon, %struct.anon* @s, i32 0, i32 1, i32 4), align 4
+  %conv6 = zext i8 %3 to i32
+  %add7 = or i32 %add5, %conv6
+  %4 = bitcast i32 %add7 to float
+  %conv8 = fpext float %4 to double
+  %call = tail call i32 (i8*, ...) @printf(i8* nonnull dereferenceable(1) getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), double %conv8)
+  ret i32 0
+}
+; Function Attrs: nofree nounwind
+declare i32 @printf(i8* nocapture readonly, ...) local_unnamed_addr