[PowerPC][LoopVectorize] Extend getRegisterClassForType to consider double and other floating point type

[jsji]

Summary

In https://reviews.llvm.org/D67148, we use isFloatTy to test floating
point type, otherwise we return GPRRC.
So 'double' will be classified as GPRRC, which is not accurate.

This patch generate different RC for other floating point types.

[merge_guards_bot]

Unit tests: pass. 61132 tests passed, 0 failed and 728 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[nemanjai]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

597–598

It seems perfectly reasonable that we want to return VSX/FPR for f32 and f64 types. However, it is not clear to me what we want to do for ppc_fp128, f128, f16, etc.

Don't get me wrong, I think the existing implementation is definitely wrong, I am just wondering if this is a complete solution.

[jsji]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

597–598

Yeah, good point.
Since most operations on ppc_f128 values become calls later, I don't think it matters much here.
While I am not sure whether we really support f16 well on PowerPC right now.

So I am preferring just leave it at it is for now.
But, yes, I am happy to accept any other suggestions.

[jsji]

Handle fp128 and fp16.

[jsji]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

597–598

OK. I have updated the code to handle f128 and f16, please have a look. Thanks.

[merge_guards_bot]

Unit tests: pass. 61144 tests passed, 0 failed and 728 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[nemanjai]

LGTM but maybe give the original author a day or two to have a look as well before committing.

[jsji]

Rebase to show changes related to this change only.

[merge_guards_bot]

Unit tests: pass. 61237 tests passed, 0 failed and 729 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

 bool PPCTTIImpl::enableInterleavedAccessVectorization() {
   return true;
 }
 
 unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
   assert(ClassID == GPRRC || ClassID == FPRRC ||
          ClassID == VRRC || ClassID == VSXRC);
   if (ST->hasVSX()) {
-    assert(ClassID == GPRRC || ClassID == VSXRC);
-    return ClassID == GPRRC ? 32 : 64;
+    assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC);
+    return ClassID == VSXRC ? 64 : 32;
   }
   assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC);
   return 32;
 }
 
 unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const {
   if (Vector)
     return ST->hasVSX() ? VSXRC : VRRC;
-  else if (Ty && Ty->getScalarType()->isFloatTy())
+  else if (Ty && (Ty->getScalarType()->isFloatTy() ||
+                  Ty->getScalarType()->isDoubleTy()))
     return ST->hasVSX() ? VSXRC : FPRRC;
+  else if (Ty && (Ty->getScalarType()->isFP128Ty() ||
+                  Ty->getScalarType()->isPPC_FP128Ty()))
+    return VRRC;
+  else if (Ty && Ty->getScalarType()->isHalfTy())
+    return VSXRC;
   else
     return GPRRC;
 }
 
 const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const {
 
   switch (ClassID) {
     default:

llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll

 ;CHECK-PWR8: LV(REG): VF = 2
 ;CHECK-PWR8: LV(REG): Found max usage: 2 item
 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
 ;CHECK-PWR8: LV(REG): Found invariant usage: 1 item
 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 1 registers
 
 ;CHECK-PWR9: LV(REG): VF = 1
-;CHECK-PWR9: LV(REG): Found max usage: 1 item
-;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 7 registers
+;CHECK-PWR9: LV(REG): Found max usage: 2 item
+;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
+;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
 ;CHECK-PWR9: LV(REG): Found invariant usage: 1 item
 ;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
 
   %1 = sext i32 %n to i64
   br label %2
 
 ; <label>:2                                       ; preds = %2, %0
   %indvars.iv = phi i64 [ %indvars.iv.next, %2 ], [ %1, %0 ]

 
 ; <label>:26                                      ; preds = %2
   ret void
 }
 
 define ppc_fp128 @fp128_(ppc_fp128* nocapture %n, ppc_fp128 %d) nounwind readonly {
 ;CHECK-LABEL: fp128_
 ;CHECK: LV(REG): VF = 1
-;CHECK: LV(REG): Found max usage: 1 item
-;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 3 registers
+;CHECK: LV(REG): Found max usage: 2 item
+;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
+;CHECK: LV(REG): RegisterClass: PPC::VRRC, 2 registers
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi ppc_fp128 [ %d, %entry ], [ %sub, %for.body ]
   %arrayidx = getelementptr inbounds ppc_fp128, ppc_fp128* %n, i32 %i.06
   %0 = load ppc_fp128, ppc_fp128* %arrayidx, align 8
   %sub = fsub ppc_fp128 %x.05, %0
   %inc = add nsw i32 %i.06, 1
   %exitcond = icmp eq i32 %inc, 2048
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
   ret ppc_fp128 %sub
 }
 
 
 define void @fp16_(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
 ;CHECK-LABEL: fp16_
 ;CHECK: LV(REG): VF = 1
-;CHECK: LV(REG): Found max usage: 1 item
-;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 5 registers
+;CHECK: LV(REG): Found max usage: 2 item
+;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 4 registers
+;CHECK: LV(REG): RegisterClass: PPC::VSXRC, 2 registers
 entry:
   %tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
   %0 = bitcast i16 %tmp.0.extract.trunc to half
   %mul = mul i32 %numCols, %numRows
   %shr = lshr i32 %mul, 2
   %cmp26 = icmp eq i32 %shr, 0
   br i1 %cmp26, label %while.end, label %while.body