[PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0

[ZhangKang]

Summary

If we didn't set the value for hasSideEffects bit in our td file, llvm-tblgen will set it as true for those instructions which has no match pattern.
Below 6 instructions don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by llvm-tblgen.

But in fact below instructions don't modify any special register and don't have other SideEffects, they shouldn't have SideEffects.
This patch is to modify the hasSideEffects of below instructions from 1 to 0.

VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX
VSPLTBs
VSPLTHs

[ZhangKang]

Modify the patch.

[lkail]

LGTM.

[Jim]

It looks like not only this 6 instructions have to set hasSideEffects to 0.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

hasSideEffects = 0 should be added class VX1_RT5_RA5_VB5.
Something like:

let hasSideEffects = 0 in
class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
...

[ZhangKang]

In D71391#1781086, @Jim wrote:

It looks like not only this 6 instructions have to set hasSideEffects to 0.

Yes, in fact, I am checking the all instructions. The 6 VSX instructions will make the case failed. And I don't want to submit a huge patch, it's hard to review, so I submitted this patch.
The other instructions fixed will in another patch.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

I don't think it is good idea to clear this flag in the format class definition, except we have clear semantics that, there won't be any side effect for all the instructions with this format. But I don't see it, though, for now, it only have six instructions instance. What do you think ?

[Jim]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

For now, It seems that VX1_RT5_RA5_VB5 is only for VEXTU* instructions. If any new instruction is added with this format, we can refactor the code for need.

[lkail]

Hi @Jim we currently prefer to set this flag at a fine grained granularity to keep it accurate, it's the purpose of sending a series of patches to perform such cleanups.

[ZhangKang]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

Yes, I will update the patch to set the hasSideEffects in VX1_RT5_RA5_VB5 .

[ZhangKang]

Set the hasSideEffects in VX1_RT5_RA5_VB5 .

[Jim]

Hi @ZhangKang
You may follow @lkail 's suggestion is fine.
I am not a PowerPC guy. Just give some suggestions.

[lkail]

In D71391#1781219, @Jim wrote:

Hi @ZhangKang
You may follow @lkail 's suggestion is fine.
I am not a PowerPC guy. Just give some suggestions.

Thanks @Jim !

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

Set the flag for the instruction format is NOT right. Please move it to the instruction definition and run the benchmark. If everything goes well, we can go with this patch.

[ZhangKang]

Set the hasSideEffect flag for on instructions instead for format.

[ZhangKang]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

Have updated the patch, I am testing the performance now.

[ZhangKang]

I have done the performance test for this patch, there is no degression.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1381

I have done the performance test for this patch, there is no degression.

[steven.zhang]

LGTM.

[jsji]

@Jim Are you intend to block this by requesting changes? If so, can you have a look again? Thanks.

[Jim]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
                       [(set v16i8:$vD,
                         (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
                       [(set v16i8:$vD,
                         (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
-let isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1, hasSideEffects = 0 in {
   def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
                          "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>;
   def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
                          "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>;
 }
 
 def VSR    : VX1_Int_Ty< 708, "vsr"  , int_ppc_altivec_vsr,  v4i32>;
 def VSRO   : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;

 
 // Vector Extract Unsigned
 def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
 def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
 def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
 def VEXTRACTD  : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
 
 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
+let hasSideEffects = 0 in {
 def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
 def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
 def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
 def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
 def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
 def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
+}
 
 // Vector Insert Element Instructions
 def VINSERTB : VXForm_1<781, (outs vrrc:$vD),
                         (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB),
                         "vinsertb $vD, $vB, $UIM", IIC_VecGeneral,
                         [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB,
                                                       imm32SExt16:$UIM))]>,
                         RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; CHECK-NEXT:    li r6, 0
 ; CHECK-NEXT:    xvnegsp v5, v0
 ; CHECK-NEXT:    xvnegsp v0, v1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    vperm v6, v1, v3, v4
 ; CHECK-NEXT:    vperm v1, v3, v1, v2
 ; CHECK-NEXT:    xvnegsp v1, v1
+; CHECK-NEXT:    add r7, r3, r4
 ; CHECK-NEXT:    xvnegsp v6, v6
 ; CHECK-NEXT:    vabsduw v1, v1, v5
 ; CHECK-NEXT:    vabsduw v6, v6, v0
 ; CHECK-NEXT:    vadduwm v1, v6, v1
 ; CHECK-NEXT:    xxswapd v6, v1
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    xxspltw v6, v1, 2
 ; CHECK-NEXT:    vadduwm v1, v1, v6
-; CHECK-NEXT:    vextuwrx r7, r5, v1
-; CHECK-NEXT:    lfdx f0, r3, r4
-; CHECK-NEXT:    add r6, r7, r6
-; CHECK-NEXT:    add r7, r3, r4
-; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    xxpermdi v6, f0, f0, 2
+; CHECK-NEXT:    vextuwrx r3, r5, v1
+; CHECK-NEXT:    vperm v7, v6, v3, v4
+; CHECK-NEXT:    vperm v6, v3, v6, v2
+; CHECK-NEXT:    add r6, r3, r6
 ; CHECK-NEXT:    add r3, r7, r4
-; CHECK-NEXT:    vperm v6, v3, v1, v2
-; CHECK-NEXT:    vperm v1, v1, v3, v4
 ; CHECK-NEXT:    xvnegsp v6, v6
-; CHECK-NEXT:    xvnegsp v1, v1
+; CHECK-NEXT:    xvnegsp v1, v7
 ; CHECK-NEXT:    vabsduw v6, v6, v5
 ; CHECK-NEXT:    vabsduw v1, v1, v0
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    xxswapd v6, v1
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    xxspltw v6, v1, 2
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    vextuwrx r8, r5, v1

 ; P9BE-NEXT:    li r6, 0
 ; P9BE-NEXT:    xvnegsp v5, v0
 ; P9BE-NEXT:    xvnegsp v0, v1
 ; P9BE-NEXT:    .p2align 4
 ; P9BE-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; P9BE-NEXT:    #
 ; P9BE-NEXT:    lfd f0, 0(r3)
 ; P9BE-NEXT:    xxlor v1, vs0, vs0
+; P9BE-NEXT:    lfdx f0, r3, r4
 ; P9BE-NEXT:    vperm v6, v3, v1, v4
 ; P9BE-NEXT:    vperm v1, v3, v1, v2
 ; P9BE-NEXT:    xvnegsp v1, v1
 ; P9BE-NEXT:    xvnegsp v6, v6
 ; P9BE-NEXT:    vabsduw v1, v1, v5
 ; P9BE-NEXT:    vabsduw v6, v6, v0
 ; P9BE-NEXT:    vadduwm v1, v6, v1
 ; P9BE-NEXT:    xxswapd v6, v1
 ; P9BE-NEXT:    vadduwm v1, v1, v6
 ; P9BE-NEXT:    xxspltw v6, v1, 1
 ; P9BE-NEXT:    vadduwm v1, v1, v6
-; P9BE-NEXT:    vextuwlx r7, r5, v1
-; P9BE-NEXT:    lfdx f0, r3, r4
-; P9BE-NEXT:    add r6, r7, r6
+; P9BE-NEXT:    xxlor v6, vs0, vs0
+; P9BE-NEXT:    vperm v7, v3, v6, v4
+; P9BE-NEXT:    vperm v6, v3, v6, v2
 ; P9BE-NEXT:    add r7, r3, r4
-; P9BE-NEXT:    xxlor v1, vs0, vs0
-; P9BE-NEXT:    add r3, r7, r4
-; P9BE-NEXT:    vperm v6, v3, v1, v2
-; P9BE-NEXT:    vperm v1, v3, v1, v4
+; P9BE-NEXT:    vextuwlx r3, r5, v1
 ; P9BE-NEXT:    xvnegsp v6, v6
-; P9BE-NEXT:    xvnegsp v1, v1
-; P9BE-NEXT:    vabsduw v6, v6, v5
+; P9BE-NEXT:    xvnegsp v1, v7
 ; P9BE-NEXT:    vabsduw v1, v1, v0
+; P9BE-NEXT:    vabsduw v6, v6, v5
 ; P9BE-NEXT:    vadduwm v1, v1, v6
 ; P9BE-NEXT:    xxswapd v6, v1
+; P9BE-NEXT:    add r6, r3, r6
 ; P9BE-NEXT:    vadduwm v1, v1, v6
 ; P9BE-NEXT:    xxspltw v6, v1, 1
 ; P9BE-NEXT:    vadduwm v1, v1, v6
 ; P9BE-NEXT:    vextuwlx r8, r5, v1
+; P9BE-NEXT:    add r3, r7, r4
 ; P9BE-NEXT:    add r6, r8, r6
 ; P9BE-NEXT:    bdnz .LBB0_1
 ; P9BE-NEXT:  # %bb.2: # %for.cond.cleanup
 ; P9BE-NEXT:    extsw r3, r6
 ; P9BE-NEXT:    blr
 entry:
   %idx.ext = sext i32 %i_stride_pix1 to i64
   %0 = bitcast i8* %pix2 to <8 x i8>*

 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test16:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 1
 ; P9BE-NEXT:    add r6, r3, r4
 ; P9BE-NEXT:    li r7, 16
 ; P9BE-NEXT:    lxsihzx v2, r6, r7
-; P9BE-NEXT:    vsplth v2, v2, 3
 ; P9BE-NEXT:    lxsihzx v4, r3, r4
 ; P9BE-NEXT:    li r6, 0
 ; P9BE-NEXT:    sldi r6, r6, 48
+; P9BE-NEXT:    vsplth v4, v4, 3
 ; P9BE-NEXT:    mtvsrd v3, r6
+; P9BE-NEXT:    vsplth v2, v2, 3
 ; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    vmrghh v2, v3, v2
-; P9BE-NEXT:    vsplth v4, v4, 3
 ; P9BE-NEXT:    vmrghh v4, v3, v4
+; P9BE-NEXT:    vmrghh v2, v3, v2
 ; P9BE-NEXT:    vsplth v3, v3, 0
 ; P9BE-NEXT:    vmrghw v3, v3, v4
 ; P9BE-NEXT:    lxvx v4, 0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vperm v2, v3, v2, v4
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3
 ; P9BE-NEXT:    vextuwlx r3, r3, v2

 
 if.end:                                           ; preds = %for.body
   ret void
 }
 
 define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxsibzx v2, r3, r4
 ; CHECK-NEXT:    add r6, r3, r4
+; CHECK-NEXT:    lxsibzx v2, r3, r4
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    mtvsrd f0, r3
 ; CHECK-NEXT:    li r3, 8
+; CHECK-NEXT:    lxsibzx v5, r6, r3
 ; CHECK-NEXT:    xxswapd v3, vs0
+; CHECK-NEXT:    vspltb v4, v3, 15
 ; CHECK-NEXT:    vspltb v2, v2, 7
-; CHECK-NEXT:    lxsibzx v5, r6, r3
-; CHECK-NEXT:    vspltb v5, v5, 7
 ; CHECK-NEXT:    vmrglb v2, v3, v2
-; CHECK-NEXT:    vspltb v4, v3, 15
-; CHECK-NEXT:    vmrglb v3, v3, v5
 ; CHECK-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    vmrglh v2, v2, v4
 ; CHECK-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-NEXT:    vspltb v5, v5, 7
+; CHECK-NEXT:    vmrglh v2, v2, v4
+; CHECK-NEXT:    vmrglb v3, v3, v5
 ; CHECK-NEXT:    vmrglw v2, v2, v4
 ; CHECK-NEXT:    vmrglh v3, v3, v4
 ; CHECK-NEXT:    vmrglw v3, v4, v3
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-NEXT:    cmpw cr0, r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test8:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add r6, r3, r4
 ; P9BE-NEXT:    li r7, 8
 ; P9BE-NEXT:    lxsibzx v2, r6, r7
-; P9BE-NEXT:    vspltb v2, v2, 7
 ; P9BE-NEXT:    lxsibzx v4, r3, r4
 ; P9BE-NEXT:    li r6, 0
 ; P9BE-NEXT:    sldi r6, r6, 56
+; P9BE-NEXT:    vspltb v4, v4, 7
 ; P9BE-NEXT:    mtvsrd v3, r6
+; P9BE-NEXT:    vspltb v2, v2, 7
+; P9BE-NEXT:    vmrghb v4, v3, v4
 ; P9BE-NEXT:    vmrghb v2, v3, v2
+; P9BE-NEXT:    vspltb v3, v3, 0
 ; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    vspltb v4, v4, 7
-; P9BE-NEXT:    vmrghb v4, v3, v4
-; P9BE-NEXT:    vspltb v3, v3, 0
 ; P9BE-NEXT:    vmrghh v4, v4, v3
 ; P9BE-NEXT:    xxspltw v3, v3, 0
 ; P9BE-NEXT:    vmrghw v2, v4, v2
 ; P9BE-NEXT:    lxvx v4, 0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vperm v2, v3, v2, v4
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3