[ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm

[chill]

Summary

The big switch in ARMBaseInstrInfo::getNumMicroOps is missing cases for
VLLDM and VLSTM, which are currently defined with itineraries having a
dynamic count of micro-ops.

Assuming an optimistic case in which these instruction do not actually perform
loads or stores, and with the idea that Armv8-m cores are supposed to use the
new style scheduling models, this patch just sets the itinerary for those two
instructions to NoItinerary.

[efriedma]

Is there some reason we can't handle these using tablegen'ed data, like other instructions?

[dmgreen]

I think that this function is only considering Itineraries? When a MISchedule isn't present? They are a bit Legacy now, and I wouldn't expect any cpu with these instructions to be using them.

It looks like in the instruction definitions, the VLSTM and VLLDM have IIC_fpLoad_m and IIC_fpStore_m. That would appear to be where the "multi-uops" is coming from. Can we just remove that? Use no itineraries instead? At the very least, like you said, the VLLDM and VLSTM are lazy so will not often not infer a cost at the point of them being ran. Maybe a NOP, if there is one? But I think None would be fine too.

[chill]

In D71266#1778483, @efriedma wrote:

Is there some reason we can't handle these using tablegen'ed data, like other instructions?

In a sense we do use tablegen, it just that tablegen says "defer that to C++ code". (cf. "dynamic uops" in ARMScheduleA8.td and ARMScheduleA9.td).

In D71266#1779054, @dmgreen wrote:

It looks like in the instruction definitions, the VLSTM and VLLDM have IIC_fpLoad_m and IIC_fpStore_m.

Yeah, I was thinking of setting these to NoItinerary. I thought I wouldn't like to disturb existing scheduling, but on a second thought,
indeed, we'd better have new-style scheduling models for armv8-m cores.

I will see about removing IIC_fpLoad, etc.

[dmgreen]

LGTM. Cheers

llvm/lib/Target/ARM/ARMInstrVFP.td

 def : MnemonicAlias<"vstm", "vstmia">;
 
 
 //===----------------------------------------------------------------------===//
 //  Lazy load / store multiple Instructions
 //
 let mayLoad = 1 in
 def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
-                  IIC_fpLoad_m, "vlldm${p}\t$Rn", "", []>,
+                  NoItinerary, "vlldm${p}\t$Rn", "", []>,
             Requires<[HasV8MMainline, Has8MSecExt]> {
     let Inst{24-23} = 0b00;
     let Inst{22}    = 0;
     let Inst{21}    = 1;
     let Inst{20}    = 1;
     let Inst{15-12} = 0;
     let Inst{7-0}   = 0;
     let mayLoad     = 1;
 }
 
 let mayStore = 1 in
 def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
-                  IIC_fpStore_m, "vlstm${p}\t$Rn", "", []>,
+                  NoItinerary, "vlstm${p}\t$Rn", "", []>,
             Requires<[HasV8MMainline, Has8MSecExt]> {
     let Inst{24-23} = 0b00;
     let Inst{22}    = 0;
     let Inst{21}    = 1;
     let Inst{20}    = 0;
     let Inst{15-12} = 0;
     let Inst{7-0}   = 0;
     let mayStore    = 1;

llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir

+# RUN: llc -run-pass=if-converter %s -o - | FileCheck %s
+--- |
+  target triple = "thumbv8m.main-arm-none-eabi"
+
+  define hidden void @foo(void ()* nocapture %baz) local_unnamed_addr #0 {
+  entry:
+    %call = call i32 @bar() #0
+    %tobool = icmp eq i32 %call, 0
+    br i1 %tobool, label %land.end, label %land.rhs
+
+  land.rhs:                                         ; preds = %entry
+    %call1 = call i32 @bar() #0
+    br label %land.end
+
+  land.end:                                         ; preds = %land.rhs, %entry
+    call void %baz() #0
+    ret void
+  }
+  declare dso_local i32 @bar() local_unnamed_addr #0
+
+  attributes #0 = { nounwind }
+
+...
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$r0' }
+frameInfo:
+  stackSize:       8
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+stack:
+  - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr',
+      callee-saved-restored: false }
+  - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r4' }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.2(0x30000000), %bb.1(0x50000000)
+    liveins: $r0, $r4, $lr
+
+    $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
+    $r4 = tMOVr $r0, 14, $noreg
+    tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
+    t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+    t2Bcc %bb.2, 0, killed $cpsr
+
+  bb.1.land.rhs:
+    liveins: $r4
+
+    tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $r0
+
+  bb.2.land.end:
+    liveins: $r4
+
+    $sp = t2STMDB_UPD $sp, 14, $noreg, $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11
+    $r4 = t2BICri $r4, 1, 14, $noreg, $noreg
+    $sp = tSUBspi $sp, 34, 14, $noreg
+    VLSTM $sp, 14, $noreg
+    tBLXNSr 14, $noreg, killed $r4, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp
+    VLLDM $sp, 14, $noreg
+    $sp = tADDspi $sp, 34, 14, $noreg
+    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
+    $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
+
+...
+# Just check there is no ICE (in debug builds)
+# CHECK: name: foo