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Differential D70968

[ARM] Enable MVE masked loads and stores
ClosedPublic

Authored by dmgreen on Dec 3 2019, 9:25 AM.

Details

Reviewers
t.p.northover
SjoerdMeijer
samparker
simon_tatham
ostannard
Commits
rGb1aba0378e52: [ARM] Enable MVE masked loads and stores
Summary

With the extra optimisations we have done, these should now be fine to enable by default. Which is what this patch does.

Diff Detail

Event Timeline

dmgreen created this revision.Dec 3 2019, 9:25 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 3 2019, 9:25 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
samparker accepted this revision.Dec 4 2019, 1:25 AM

Definitely!

This revision is now accepted and ready to land.Dec 4 2019, 1:25 AM
Closed by commit rGb1aba0378e52: [ARM] Enable MVE masked loads and stores (authored by dmgreen). · Explain WhyDec 9 2019, 3:43 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 232803

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

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#include <cstdint> #include <cstdint>
#include <utility> #include <utility>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "armtti" #define DEBUG_TYPE "armtti"
static cl::opt<bool> EnableMaskedLoadStores( static cl::opt<bool> EnableMaskedLoadStores(
"enable-arm-maskedldst", cl::Hidden, cl::init(false), "enable-arm-maskedldst", cl::Hidden, cl::init(true),
cl::desc("Enable the generation of masked loads and stores")); cl::desc("Enable the generation of masked loads and stores"));
static cl::opt<bool> DisableLowOverheadLoops( static cl::opt<bool> DisableLowOverheadLoops(
"disable-arm-loloops", cl::Hidden, cl::init(false), "disable-arm-loloops", cl::Hidden, cl::init(false),
cl::desc("Disable the generation of low-overhead loops")); cl::desc("Disable the generation of low-overhead loops"));
extern cl::opt<bool> DisableTailPredication; extern cl::opt<bool> DisableTailPredication;
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll

; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -enable-arm-maskedldst=true -disable-mve-tail-predication=false --verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false --verify-machineinstrs %s -o - | FileCheck %s
; CHECK-LABEL: vpsel_mul_reduce_add ; CHECK-LABEL: vpsel_mul_reduce_add
; CHECK: dls lr, lr ; CHECK: dls lr, lr
; CHECK: [[LOOP:.LBB[0-9_]+]]: ; CHECK: [[LOOP:.LBB[0-9_]+]]:
; CHECK: vctp.32 [[ELEMS:r[0-9]+]] ; CHECK: vctp.32 [[ELEMS:r[0-9]+]]
; CHECK: mov [[ELEMS_OUT:r[0-9]+]], [[ELEMS]] ; CHECK: mov [[ELEMS_OUT:r[0-9]+]], [[ELEMS]]
; CHECK: vstr p0, [sp ; CHECK: vstr p0, [sp
; CHECK: vpstt ; CHECK: vpstt
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16 -enable-arm-maskedldst=true -disable-mve-tail-predication=false %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16 -disable-mve-tail-predication=false %s -o - | FileCheck %s
define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocapture readonly %b, float* nocapture readonly %c, i32 %N) { define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocapture readonly %b, float* nocapture readonly %c, i32 %N) {
; CHECK-LABEL: fast_float_mul: ; CHECK-LABEL: fast_float_mul:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB0_11 ; CHECK-NEXT: beq.w .LBB0_11
; CHECK-NEXT: @ %bb.1: @ %vector.memcheck ; CHECK-NEXT: @ %bb.1: @ %vector.memcheck
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false -enable-arm-maskedldst=true %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false %s -o - | FileCheck %s
define arm_aapcs_vfpcc i32 @test_acc_scalar_char(i8 zeroext %a, i8* nocapture readonly %b, i32 %N) { define arm_aapcs_vfpcc i32 @test_acc_scalar_char(i8 zeroext %a, i8* nocapture readonly %b, i32 %N) {
; CHECK-LABEL: test_acc_scalar_char: ; CHECK-LABEL: test_acc_scalar_char:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: itt eq ; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r0, #0 ; CHECK-NEXT: moveq r0, #0
; CHECK-NEXT: bxeq lr ; CHECK-NEXT: bxeq lr
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -enable-arm-maskedldst=true -disable-mve-tail-predication=false --verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -disable-mve-tail-predication=false --verify-machineinstrs %s -o - | FileCheck %s
define dso_local i32 @mul_reduce_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32 %N) { define dso_local i32 @mul_reduce_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32 %N) {
; CHECK-LABEL: mul_reduce_add: ; CHECK-LABEL: mul_reduce_add:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: itt eq ; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r0, #0 ; CHECK-NEXT: moveq r0, #0
; CHECK-NEXT: bxeq lr ; CHECK-NEXT: bxeq lr
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llvm/test/CodeGen/Thumb2/mve-intrinsics/load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -enable-arm-maskedldst -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(half* %base) { define arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(half* %base) {
; CHECK-LABEL: test_vld1q_f16: ; CHECK-LABEL: test_vld1q_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast half* %base to <8 x half>* %0 = bitcast half* %base to <8 x half>*
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llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: vpt.i32 ne, q0, zr ; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vldrwt.u32 q0, [r0, #4] ; CHECK-NEXT: vldrwt.u32 q0, [r0, #4]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
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llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: vpt.i32 ne, q0, zr ; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vldrwt.u32 q0, [r0], #4 ; CHECK-NEXT: vldrwt.u32 q0, [r0], #4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
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llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: vpt.i32 ne, q0, zr ; CHECK-NEXT: vpt.i32 ne, q0, zr
; CHECK-NEXT: vldrwt.u32 q0, [r0, #4]! ; CHECK-NEXT: vldrwt.u32 q0, [r0, #4]!
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
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llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define void @foo_v4i32_v4i32(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i32> *%src) { define void @foo_v4i32_v4i32(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
; CHECK-LABEL: foo_v4i32_v4i32: ; CHECK-LABEL: foo_v4i32_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vptt.s32 gt, q0, zr ; CHECK-NEXT: vptt.s32 gt, q0, zr
; CHECK-NEXT: vldrwt.u32 q0, [r2] ; CHECK-NEXT: vldrwt.u32 q0, [r2]
; CHECK-NEXT: vstrwt.32 q0, [r0] ; CHECK-NEXT: vstrwt.32 q0, [r0]
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llvm/test/CodeGen/Thumb2/mve-masked-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(<4 x i32> *%dest, <4 x i32> %a) { define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(<4 x i32> *%dest, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4i32_align4_zero: ; CHECK-LE-LABEL: masked_v4i32_align4_zero:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vldrwt.u32 q0, [r0] ; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
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llvm/test/CodeGen/Thumb2/mve-masked-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) { define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4i32: ; CHECK-LE-LABEL: masked_v4i32:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vstrwt.32 q0, [r0] ; CHECK-LE-NEXT: vstrwt.32 q0, [r0]
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
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llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll

; RUN: opt -loop-vectorize -enable-arm-maskedldst < %s -S -o - | FileCheck %s ; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1-m.main-none-eabi" target triple = "thumbv8.1-m.main-none-eabi"
; CHECK-LABEL: test_i32_align4 ; CHECK-LABEL: test_i32_align4
; CHECK: call void @llvm.masked.store.v4i32.p0v4i32 ; CHECK: call void @llvm.masked.store.v4i32.p0v4i32
define void @test_i32_align4(i32* nocapture %A, i32 %n) #0 { define void @test_i32_align4(i32* nocapture %A, i32 %n) #0 {
entry: entry:
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llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll

; RUN: opt -loop-vectorize -enable-arm-maskedldst < %s -S -o - | FileCheck %s --check-prefix=CHECK ; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s --check-prefix=CHECK
; RUN: opt -loop-vectorize -enable-arm-maskedldst -debug-only=loop-vectorize -disable-output < %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST ; RUN: opt -loop-vectorize -debug-only=loop-vectorize -disable-output < %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi" target triple = "thumbv8.1m.main-arm-none-eabi"
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK-COST: LV: Found an estimated cost of 0 for VF 1 For instruction: %and515 = shl i32 %l41, 3 ; CHECK-COST: LV: Found an estimated cost of 0 for VF 1 For instruction: %and515 = shl i32 %l41, 3
; CHECK-COST: LV: Found an estimated cost of 1 for VF 1 For instruction: %l45 = and i32 %and515, 131072 ; CHECK-COST: LV: Found an estimated cost of 1 for VF 1 For instruction: %l45 = and i32 %and515, 131072
; CHECK-COST: LV: Found an estimated cost of 2 for VF 4 For instruction: %and515 = shl i32 %l41, 3 ; CHECK-COST: LV: Found an estimated cost of 2 for VF 4 For instruction: %and515 = shl i32 %l41, 3
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llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll

; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf \ ; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf \
; RUN: -disable-mve-tail-predication=false -loop-vectorize -S < %s | \ ; RUN: -disable-mve-tail-predication=false -loop-vectorize -S < %s | \
; RUN: FileCheck %s -check-prefixes=CHECK,NO-FOLDING ; RUN: FileCheck %s -check-prefixes=CHECK,PREFER-FOLDING
; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=-mve \ ; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=-mve \
; RUN: -disable-mve-tail-predication=false -loop-vectorize \ ; RUN: -disable-mve-tail-predication=false -loop-vectorize \
; RUN: -enable-arm-maskedldst=true -S < %s | \ ; RUN: -enable-arm-maskedldst=true -S < %s | \
; RUN: FileCheck %s -check-prefixes=CHECK,NO-FOLDING ; RUN: FileCheck %s -check-prefixes=CHECK,NO-FOLDING
; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=+mve \ ; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=+mve \
; RUN: -disable-mve-tail-predication=false -loop-vectorize \ ; RUN: -disable-mve-tail-predication=false -loop-vectorize \
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llvm/test/Transforms/LoopVectorize/ARM/tail-loop-folding.ll

; RUN: opt < %s -loop-vectorize -enable-arm-maskedldst -S | \ ; RUN: opt < %s -loop-vectorize -S | \
; RUN: FileCheck %s -check-prefixes=COMMON,CHECK ; RUN: FileCheck %s -check-prefixes=COMMON,CHECK
; RUN: opt < %s -loop-vectorize -enable-arm-maskedldst -prefer-predicate-over-epilog -S | \ ; RUN: opt < %s -loop-vectorize -prefer-predicate-over-epilog -S | \
; RUN: FileCheck -check-prefixes=COMMON,PREDFLAG %s ; RUN: FileCheck -check-prefixes=COMMON,PREDFLAG %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-unknown-eabihf" target triple = "thumbv8.1m.main-arm-unknown-eabihf"
define dso_local void @tail_folding(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C) #0 { define dso_local void @tail_folding(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C) #0 {
; CHECK-LABEL: tail_folding( ; CHECK-LABEL: tail_folding(
; CHECK: vector.body: ; CHECK: vector.body:
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