[ARM] Fix instruction selection for ARMISD::CMOV with f16 type

[vhscampos]

Summary

In the cases where the CMOV (f16) SDNode is used with condition codes
LT, LE, VC or NE, it is successfully selected into a VSEL instruction.

In the remaining cases, however, instruction selection fails since VSEL
does not support other condition codes.

This patch handles such cases by using the single-precision version of
the VMOV instruction.

[vhscampos]

Now using a pseudo instruction instead, VMOVHcc, which is lowered into a single-precision VMOV.

[dmgreen]

Yeah I think ran into this on one or two of the MVE cases.

Looks sensible to me, with a minor point about HasFPRegs.

llvm/lib/Target/ARM/ARMInstrVFP.td

2287 ↗

(On Diff #231264)

If this is ending up as a VMOVS, it can actually be HasFPRegs? I guess it shouldn't matter though, if we are not ever selecting the ARMcmov for an fp16.

The itinerary could also be IIC_fpUNA32, but I don't think they will really be used anywhere or make much of a difference.

If HasFPRegs looks like it will cause problems in any way, then HasFPRegs16 would be fine too.

[vhscampos]

Require single-precision floating-point registers instead.

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (!Subtarget->hasFP64() && VT == MVT::f64) {
     SDValue FalseHigh = FalseVal.getValue(1);
 
     SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
                               ARMcc, CCR, Cmp);
     SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
                                ARMcc, CCR, duplicateCmp(Cmp, DAG));
 
     return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
+  } else if (VT == MVT::f16) {
+    uint64_t CC = cast<ConstantSDNode>(ARMcc)->getZExtValue();
+    // CMOV can be selected only for the following condition codes. In the
+    // remaining cases, values are bitcast to and from i32 to make selection
+    // possible.
+    if (CC == ARMCC::GT || CC == ARMCC::GE || CC == ARMCC::EQ ||
+        CC == ARMCC::VS) {
+      return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
+                         Cmp);
+    } else {
+      FalseVal = DAG.getNode(ARMISD::VMOVrh, dl, MVT::i32, FalseVal);
+      TrueVal = DAG.getNode(ARMISD::VMOVrh, dl, MVT::i32, TrueVal);
+      SDValue CMOV = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseVal, TrueVal,
+                                 ARMcc, CCR, Cmp);
+      return DAG.getNode(ARMISD::VMOVhr, dl, MVT::f16, CMOV);
+    }
   } else {
     return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
                        Cmp);
   }
 }
 
 static bool isGTorGE(ISD::CondCode CC) {
   return CC == ISD::SETGT || CC == ISD::SETGE;

llvm/test/CodeGen/ARM/cmov_fp16.ll

+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 %s -filetype=null -o -
+; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -filetype=null -o -
+
+define i32 @foo(i32 %x, i32 %y, i32 %a, i32 %b) #0 {
+entry:
+  %x.half = uitofp i32 %x to half
+  %y.half = uitofp i32 %y to half
+  %cmp = icmp ult i32 %a, %b
+  %cond = select i1 %cmp, half %x.half, half %y.half
+  %0 = bitcast half %cond to i16
+  %1 = zext i16 %0 to i32
+  ret i32 %1
+}