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AMDGPU: Reuse carry out register during FI elimination
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Authored by kerbowa on Nov 22 2019, 1:00 PM.

Details

Summary

Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add.
If only one SGPR was available this crashed when trying to scavenge another
32bit SGPR to materialize the offset.

Instead, reuse a 32-bit SGPR from the carry out as the offset register.

Also prefer to use vcc for the unused carry out when it is available.

Event Timeline

kerbowa created this revision.Nov 22 2019, 1:00 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 22 2019, 1:00 PM
rampitec added inline comments.Nov 22 2019, 1:20 PM
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
6216

RI.getVCC(), even though right now we cannot hit this with wave32.

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
1130

It ignores wave32 where carry is 32 bit. Granted right now we have no carry adds on all GFX10, but we cannot be sure this will be the same in the future. At least assert if needed the register is 64 bit.

kerbowa updated this revision to Diff 230724.Nov 22 2019, 2:18 PM

Don't assume 64bit carry out.

This revision is now accepted and ready to land.Nov 22 2019, 2:32 PM
arsenm added inline comments.Nov 22 2019, 7:43 PM
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
1136

It would be slightly safer to directly check wave32 or not than relying on getting the physreg class and directly checking it. Sometimes the exact subclass changes

This revision was automatically updated to reflect the committed changes.
kerbowa marked an inline comment as done.