[InstCombine] Infer fast math flags on fadd/fsub/fmul/fcmp

[bkramer]

Summary

Applies nnan, ninf and nsz. This allows more instructions to be folded
away even with no fast math flags, e.g. (int)x * (b ? 1.0 : 0.0) -> b ? x : 0.0

As a side effect this will propagate fast math flags out of inlined fast
math code into surrounding functions.

[bkramer]

Fix condition

[spatel]

I like the idea, but I'd be more comfortable reviewing the diffs in stages, so we know that the test coverage for the value tracking calls is good. So I'd prefer if we split this somehow - either by the opcode callers (fadd, fsub, fmul...) or the the FMF analysis (nnan, nsz, ninf). That raises a few questions:

1. Why aren't fdiv and frem included?
2. Can we infer FMF for FP intrinsics/libcalls/select/phi? (follow-on patches)
3. We're moving away from FMF on fcmp (recent step: rGebf9bf2cbc8f), so is it worth including starting from fcmp, or can we wait for that part to settle? (Side question may be if/when we're going to allow FMF on fptrunc/fpextend).

[mcberg2017]

For us this would be an impediment as we have math models that want ieee behavior while relaxing precision. Adding nnan or ninf would obstruct those choices.

[bkramer]

In D70488#1753897, @mcberg2017 wrote:

For us this would be an impediment as we have math models that want ieee behavior while relaxing precision. Adding nnan or ninf would obstruct those choices.

Mind elaborating why nnan/ninf are problematic for you? They're supposed to be a hint to the optimizer and can be dropped any time.

In D70488#1753832, @spatel wrote:

I like the idea, but I'd be more comfortable reviewing the diffs in stages, so we know that the test coverage for the value tracking calls is good. So I'd prefer if we split this somehow - either by the opcode callers (fadd, fsub, fmul...) or the the FMF analysis (nnan, nsz, ninf). That raises a few questions:

1. Why aren't fdiv and frem included?

We currently cannot infer anything for fdiv/frem in isKnownNeverNaN/Inf so there's no way to test it.

2. Can we infer FMF for FP intrinsics/libcalls/select/phi? (follow-on patches)

Yeah, that's a logical followup

3. We're moving away from FMF on fcmp (recent step: rGebf9bf2cbc8f), so is it worth including starting from fcmp, or can we wait for that part to settle? (Side question may be if/when we're going to allow FMF on fptrunc/fpextend).

I'll drop fcmp then and split this up once we know that it's actually a direction we want to pursue.

clang/test/CodeGen/builtins-systemz-zvector.c

void test_float(void) {
   // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
   // (emulated)
   vd = vec_ctd(vsl, 1);
   // CHECK: [[VAL:%[^ ]+]] = sitofp <2 x i64> %{{.*}} to <2 x double>
   // CHECK: fmul <2 x double> [[VAL]], <double 5.000000e-01, double 5.000000e-01>
   // (emulated)
   vd = vec_ctd(vul, 1);
   // CHECK: [[VAL:%[^ ]+]] = uitofp <2 x i64> %{{.*}} to <2 x double>
-  // CHECK: fmul <2 x double> [[VAL]], <double 5.000000e-01, double 5.000000e-01>
+  // CHECK: fmul nnan <2 x double> [[VAL]], <double 5.000000e-01, double 5.000000e-01>
   // (emulated)
   vd = vec_ctd(vsl, 31);
   // CHECK: [[VAL:%[^ ]+]] = sitofp <2 x i64> %{{.*}} to <2 x double>
   // CHECK: fmul <2 x double> [[VAL]], <double 0x3E00000000000000, double 0x3E00000000000000>
   // (emulated)
   vd = vec_ctd(vul, 31);
   // CHECK: [[VAL:%[^ ]+]] = uitofp <2 x i64> %{{.*}} to <2 x double>
-  // CHECK: fmul <2 x double> [[VAL]], <double 0x3E00000000000000, double 0x3E00000000000000>
+  // CHECK: fmul nnan <2 x double> [[VAL]], <double 0x3E00000000000000, double 0x3E00000000000000>
   // (emulated)
 
   vsl = vec_ctsl(vd, 0);
   // CHECK: fptosi <2 x double> %{{.*}} to <2 x i64>
   // (emulated)
   vul = vec_ctul(vd, 0);
   // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>
   // (emulated)

llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

Instruction *InstCombiner::visitFAdd(BinaryOperator &I) {
 
   if (I.hasAllowReassoc() && I.hasNoSignedZeros()) {
     if (Instruction *F = factorizeFAddFSub(I, Builder))
       return F;
     if (Value *V = FAddCombine(Builder).simplify(&I))
       return replaceInstUsesWith(I, V);
   }
 
-  return nullptr;
+  return inferFastMathFlags(&I, {&I, I.getOperand(0), I.getOperand(1)})
+             ? &I
+             : nullptr;
 }
 
 /// Optimize pointer differences into the same array into a size.  Consider:
 ///  &A[10] - &A[0]: we should compile this to "10".  LHS/RHS are the pointer
 /// operands to the ptrtoint instructions for the LHS/RHS of the subtract.
 Value *InstCombiner::OptimizePointerDifference(Value *LHS, Value *RHS,
                                                Type *Ty) {
   // If LHS is a gep based on RHS or RHS is a gep based on LHS, we can optimize
if (I.hasAllowReassoc() && I.hasNoSignedZeros()) {
     // TODO: This performs reassociative folds for FP ops. Some fraction of the
     // functionality has been subsumed by simple pattern matching here and in
     // InstSimplify. We should let a dedicated reassociation pass handle more
     // complex pattern matching and remove this from InstCombine.
     if (Value *V = FAddCombine(Builder).simplify(&I))
       return replaceInstUsesWith(I, V);
   }
 
-  return nullptr;
+  return inferFastMathFlags(&I, {&I, I.getOperand(0), I.getOperand(1)})
+             ? &I
+             : nullptr;
 }

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

if (match(Op1, m_APFloat(C))) {
       }
     }
   }
 
   if (I.getType()->isVectorTy())
     if (Instruction *Res = foldVectorCmp(I, Builder))
       return Res;
 
+  // Set fast math flags if both operands are compatible.
+  Changed |= inferFastMathFlags(&I, {I.getOperand(0), I.getOperand(1)});
+
   return Changed ? &I : nullptr;
 }

llvm/lib/Transforms/InstCombine/InstCombineInternal.h

private:
 
   Value *foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS,
                                        bool JoinedByAnd, Instruction &CxtI);
   Value *matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D);
   Value *getSelectCondition(Value *A, Value *B);
 
   Instruction *foldIntrinsicWithOverflowCommon(IntrinsicInst *II);
 
+  /// Add fast math flags to the instruction if all Values statisfy the
+  /// constraints required by the flag, returning true if the instruction
+  /// was changed.
+  bool inferFastMathFlags(Instruction *I, ArrayRef<Value*> Values) const;
+
 public:
   /// Inserts an instruction \p New before instruction \p Old
   ///
   /// Also adds the new instruction to the worklist and returns \p New so that
   /// it is suitable for use as the return from the visitation patterns.
   Instruction *InsertNewInstBefore(Instruction *New, Instruction &Old) {
     assert(New && !New->getParent() &&
            "New instruction already inserted into a basic block!");

llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

if (I.isFast()) {
     if (Log2) {
       Log2->setArgOperand(0, X);
       Log2->copyFastMathFlags(&I);
       Value *LogXTimesY = Builder.CreateFMulFMF(Log2, Y, &I);
       return BinaryOperator::CreateFSubFMF(LogXTimesY, Y, &I);
     }
   }
 
-  return nullptr;
+  return inferFastMathFlags(&I, {&I, I.getOperand(0), I.getOperand(1)})
+             ? &I
+             : nullptr;
 }
 
 /// Fold a divide or remainder with a select instruction divisor when one of the
 /// select operands is zero. In that case, we can use the other select operand
 /// because div/rem by zero is undefined.
 bool InstCombiner::simplifyDivRemOfSelectWithZeroOp(BinaryOperator &I) {
   SelectInst *SI = dyn_cast<SelectInst>(I.getOperand(1));
   if (!SI)

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

if (auto *NewBinOp = dyn_cast<BinaryOperator>(NarrowBO)) {
     if (IsSext)
       NewBinOp->setHasNoSignedWrap();
     else
       NewBinOp->setHasNoUnsignedWrap();
   }
   return CastInst::Create(CastOpc, NarrowBO, BO.getType());
 }
 
+bool InstCombiner::inferFastMathFlags(Instruction *I, ArrayRef<Value*> Values) const {
+  bool Changed = false;
+  if (!I->hasNoInfs() &&
+      all_of(Values, [&](Value *V) { return isKnownNeverInfinity(V, &TLI); })) {
+    I->setHasNoInfs(true);
+    Changed = true;
+  }
+
+  if (!I->hasNoNaNs() &&
+      all_of(Values, [&](Value *V) { return isKnownNeverNaN(V, &TLI); })) {
+    I->setHasNoNaNs(true);
+    Changed = true;
+  }
+
+  if (!I->hasNoSignedZeros() &&
+      all_of(Values, [&](Value *V) { return CannotBeNegativeZero(V, &TLI); })) {
+    I->setHasNoSignedZeros(true);
+    Changed = true;
+  }
+
+  return Changed;
+}
+
 Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
   SmallVector<Value*, 8> Ops(GEP.op_begin(), GEP.op_end());
   Type *GEPType = GEP.getType();
   Type *GEPEltType = GEP.getSourceElementType();
   if (Value *V = SimplifyGEPInst(GEPEltType, Ops, SQ.getWithInstruction(&GEP)))
     return replaceInstUsesWith(GEP, V);
 
   // For vector geps, use the generic demanded vector support.

llvm/test/Transforms/InstCombine/add-sitofp.ll

;
   %res = fadd double %a_and_fp, 1.0
   ret double %res
 }
 
 define float @test_neg(i32 %a) {
 ; CHECK-LABEL: @test_neg(
 ; CHECK-NEXT:    [[A_AND:%.*]] = and i32 [[A:%.*]], 1073741823
 ; CHECK-NEXT:    [[A_AND_FP:%.*]] = sitofp i32 [[A_AND]] to float
-; CHECK-NEXT:    [[RES:%.*]] = fadd float [[A_AND_FP]], 1.000000e+00
+; CHECK-NEXT:    [[RES:%.*]] = fadd nnan float [[A_AND_FP]], 1.000000e+00
 ; CHECK-NEXT:    ret float [[RES]]
 ;
   ; Drop two highest bits to guarantee that %a + 1 doesn't overflow
   %a_and = and i32 %a, 1073741823
   %a_and_fp = sitofp i32 %a_and to float
   %res = fadd float %a_and_fp, 1.0
   ret float %res
 }

 ; This test demonstrates overly conservative legality check. The float addition
 ; can be replaced with the integer addition because the result of the operation
 ; can be represented in float, but we don't do that now.
 define float @test_3(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test_3(
 ; CHECK-NEXT:    [[M:%.*]] = lshr i32 [[A:%.*]], 24
 ; CHECK-NEXT:    [[N:%.*]] = and i32 [[M]], [[B:%.*]]
 ; CHECK-NEXT:    [[O:%.*]] = sitofp i32 [[N]] to float
-; CHECK-NEXT:    [[P:%.*]] = fadd float [[O]], 1.000000e+00
+; CHECK-NEXT:    [[P:%.*]] = fadd nnan float [[O]], 1.000000e+00
 ; CHECK-NEXT:    ret float [[P]]
 ;
   %m = lshr i32 %a, 24
   %n = and i32 %m, %b
   %o = sitofp i32 %n to float
   %p = fadd float %o, 1.0
   ret float %p
 }

llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll

;
   %f = sitofp i64 %i to half
   %cmp = fcmp oeq half %f, 0.0
   ret i1 %cmp
 }
 
 define i1 @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(
 ; CHECK-NEXT:    [[F:%.*]] = uitofp i32 [[I:%.*]] to ppc_fp128
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq ppc_fp128 [[F]], 0xM00000000000000000000000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan ninf nsz oeq ppc_fp128 [[F]], 0xM00000000000000000000000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = uitofp i32 %i to ppc_fp128
   %cmp = fcmp oeq ppc_fp128 %f, 0xM00000000000000000000000000000000
   ret i1 %cmp
 }
 
 ; Since 0xFFFFFF fits in a float, and one less and

 ; Though 0x1000000 fits in a float, one more than it
 ; would round to it too, hence a single integer comparison
 ; does not suffice.
 
 
 define i1 @i32_cast_cmp_oeq_int_i24maxp1_uitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_uitofp(
 ; CHECK-NEXT:    [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x4170000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan ninf nsz oeq float [[F]], 0x4170000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = uitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x4170000000000000
   ret i1 %cmp
 }
 
 
 define i1 @i32_cast_cmp_oeq_int_i24maxp1_sitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_sitofp(
 ; CHECK-NEXT:    [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x4170000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan nsz oeq float [[F]], 0x4170000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = sitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x4170000000000000
   ret i1 %cmp
 }
 
 define i1 @i32_cast_cmp_oeq_int_i32umax_uitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32umax_uitofp(
 ; CHECK-NEXT:    [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x41F0000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan ninf nsz oeq float [[F]], 0x41F0000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = uitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x41F0000000000000
   ret i1 %cmp
 }
 
 ; 32-bit unsigned integer cannot possibly round up to 1<<33
;
   %f = sitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x41F0000000000000
   ret i1 %cmp
 }
 
 define i1 @i32_cast_cmp_oeq_int_i32imin_sitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imin_sitofp(
 ; CHECK-NEXT:    [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0xC1E0000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan nsz oeq float [[F]], 0xC1E0000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = sitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0xC1E0000000000000
   ret i1 %cmp
 }
 
 define i1 @i32_cast_cmp_oeq_int_i32imax_uitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_uitofp(
 ; CHECK-NEXT:    [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x41E0000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan ninf nsz oeq float [[F]], 0x41E0000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = uitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x41E0000000000000
   ret i1 %cmp
 }
 
 define i1 @i32_cast_cmp_oeq_int_i32imax_sitofp(i32 %i) {
 ; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_sitofp(
 ; CHECK-NEXT:    [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x41E0000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan nsz oeq float [[F]], 0x41E0000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = sitofp i32 %i to float
   %cmp = fcmp oeq float %f, 0x41E0000000000000
   ret i1 %cmp
 }
 
 ; 32-bit signed integer cannot possibly round to -1<<32
;
   %cmp = fcmp oeq float %f, 0x7FF0000000000000
   ret i1 %cmp
 }
 
 ; An i128 could round to an IEEE single-precision infinity.
 define i1 @i128_cast_cmp_oeq_int_inf_uitofp(i128 %i) {
 ; CHECK-LABEL: @i128_cast_cmp_oeq_int_inf_uitofp(
 ; CHECK-NEXT:    [[F:%.*]] = uitofp i128 [[I:%.*]] to float
-; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq float [[F]], 0x7FF0000000000000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp nnan nsz oeq float [[F]], 0x7FF0000000000000
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %f = uitofp i128 %i to float
   %cmp = fcmp oeq float %f, 0x7FF0000000000000
   ret i1 %cmp
 }

llvm/test/Transforms/InstCombine/fadd-fsub-factor.ll

 }
 
 ; Negative test - verify the fold is not done with only 'reassoc' ('nsz' is required).
 
 define float @fmul_fadd_not_enough_FMF(float %x, float %y, float %z) {
 ; CHECK-LABEL: @fmul_fadd_not_enough_FMF(
 ; CHECK-NEXT:    [[T1:%.*]] = fmul fast float [[X:%.*]], [[Z:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = fmul fast float [[Y:%.*]], [[Z]]
-; CHECK-NEXT:    [[R:%.*]] = fadd reassoc float [[T1]], [[T2]]
+; CHECK-NEXT:    [[R:%.*]] = fadd reassoc nnan float [[T1]], [[T2]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
   %t1 = fmul fast float %x, %z
   %t2 = fmul fast float %y, %z
   %r = fadd reassoc float %t1, %t2
   ret float %r
 }
 

 }
 
 ; Negative test - verify the fold is not done with only 'nsz' ('reassoc' is required).
 
 define float @fmul_fsub_not_enough_FMF(float %x, float %y, float %z) {
 ; CHECK-LABEL: @fmul_fsub_not_enough_FMF(
 ; CHECK-NEXT:    [[T1:%.*]] = fmul fast float [[Z:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = fmul fast float [[Y:%.*]], [[Z]]
-; CHECK-NEXT:    [[R:%.*]] = fsub nsz float [[T1]], [[T2]]
+; CHECK-NEXT:    [[R:%.*]] = fsub nnan nsz float [[T1]], [[T2]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
   %t1 = fmul fast float %z, %x
   %t2 = fmul fast float %y, %z
   %r = fsub nsz float %t1, %t2
   ret float %r
 }
 

 }
 
 ; Negative test - verify the fold is not done with only 'nsz' ('reassoc' is required).
 
 define float @fdiv_fadd_not_enough_FMF(float %x, float %y, float %z) {
 ; CHECK-LABEL: @fdiv_fadd_not_enough_FMF(
 ; CHECK-NEXT:    [[T1:%.*]] = fdiv fast float [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = fdiv fast float [[Z:%.*]], [[X]]
-; CHECK-NEXT:    [[T3:%.*]] = fadd nsz float [[T1]], [[T2]]
+; CHECK-NEXT:    [[T3:%.*]] = fadd nnan nsz float [[T1]], [[T2]]
 ; CHECK-NEXT:    ret float [[T3]]
 ;
   %t1 = fdiv fast float %y, %x
   %t2 = fdiv fast float %z, %x
   %t3 = fadd nsz float %t1, %t2
   ret float %t3
 }
 
 ; Negative test - verify the fold is not done with only 'reassoc' ('nsz' is required).
 
 define float @fdiv_fsub_not_enough_FMF(float %x, float %y, float %z) {
 ; CHECK-LABEL: @fdiv_fsub_not_enough_FMF(
 ; CHECK-NEXT:    [[T1:%.*]] = fdiv fast float [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = fdiv fast float [[Z:%.*]], [[X]]
-; CHECK-NEXT:    [[T3:%.*]] = fsub reassoc float [[T1]], [[T2]]
+; CHECK-NEXT:    [[T3:%.*]] = fsub reassoc nnan float [[T1]], [[T2]]
 ; CHECK-NEXT:    ret float [[T3]]
 ;
   %t1 = fdiv fast float %y, %x
   %t2 = fdiv fast float %z, %x
   %t3 = fsub reassoc float %t1, %t2
   ret float %t3
 }
 

llvm/test/Transforms/InstCombine/fast-math.ll

;
   ret float %mul1
 }
 
 ; Same testing-case as the one used in fold() except that the operators have
 ; fixed FP mode.
 define float @notfold(float %a) {
 ; CHECK-LABEL: @notfold(
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul fast float [[A:%.*]], 0x3FF3333340000000
-; CHECK-NEXT:    [[MUL1:%.*]] = fmul float [[MUL]], 0x4002666660000000
+; CHECK-NEXT:    [[MUL1:%.*]] = fmul nnan float [[MUL]], 0x4002666660000000
 ; CHECK-NEXT:    ret float [[MUL1]]
 ;
   %mul = fmul fast float %a, 0x3FF3333340000000
   %mul1 = fmul float %mul, 0x4002666660000000
   ret float %mul1
 }
 
 define float @fold2(float %a) {

llvm/test/Transforms/InstCombine/fcmp.ll

;
   %div = fdiv ninf float -1.0, %X
   %cmp = fcmp ninf oge float %div, 0.0
   ret i1 %cmp
 }
 
 ; Do not fold 1.0 / X > 0.0 when ninf is missing
 define i1 @test24_recipX_noninf_cmp(float %X) {
 ; CHECK-LABEL: @test24_recipX_noninf_cmp(
-; CHECK-NEXT:    [[DIV:%.*]] = fdiv ninf float 2.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = fdiv float 2.000000e+00, [[X:%.*]]
 ; CHECK-NEXT:    [[CMP:%.*]] = fcmp ogt float [[DIV]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
-  %div = fdiv ninf float 2.0, %X
+  %div = fdiv float 2.0, %X
   %cmp = fcmp ogt float %div, 0.0
   ret i1 %cmp
 }
 
 ; Do not fold 1.0 / X > 0.0 when ninf is missing
 define i1 @test25_recipX_noninf_div(float %X) {
 ; CHECK-LABEL: @test25_recipX_noninf_div(
 ; CHECK-NEXT:    [[DIV:%.*]] = fdiv float 2.000000e+00, [[X:%.*]]

llvm/test/Transforms/InstCombine/known-never-nan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -instcombine | FileCheck %s
 
 ; This file used to contain more tests that folded to true/false,
 ; but those are all tested identically in InstSimplify now.
 ; If any remaining tests are made to return true/false, that
 ; functionality/testing may be better housed in InstSimplify
 ; rather than InstCombine.
 
 define i1 @fabs_sqrt_src_maybe_nan(double %arg0, double %arg1) {
 ; CHECK-LABEL: @fabs_sqrt_src_maybe_nan(
 ; CHECK-NEXT:    [[FABS:%.*]] = call double @llvm.fabs.f64(double [[ARG0:%.*]])
 ; CHECK-NEXT:    [[OP:%.*]] = call double @llvm.sqrt.f64(double [[FABS]])
-; CHECK-NEXT:    [[TMP:%.*]] = fcmp ord double [[OP]], 0.000000e+00
+; CHECK-NEXT:    [[TMP:%.*]] = fcmp nsz ord double [[OP]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[TMP]]
 ;
   %fabs = call double @llvm.fabs.f64(double %arg0)
   %op = call double @llvm.sqrt.f64(double %fabs)
   %tmp = fcmp ord double %op, %op
   ret i1 %tmp
 }
 

llvm/test/Transforms/InstCombine/minmax-fp.ll

;
   %max = select i1 %cond, float %n1, float %n2
   ret float %max
 }
 
 define <2 x float> @fsub_fmax(<2 x float> %x, <2 x float> %y) {
 ; CHECK-LABEL: define {{[^@]+}}@fsub_fmax(
 ; CHECK-NEXT:    [[COND_INV:%.*]] = fcmp nnan nsz ogt <2 x float> [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = select nnan nsz <2 x i1> [[COND_INV]], <2 x float> [[Y]], <2 x float> [[X]]
-; CHECK-NEXT:    [[MAX:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, [[TMP1]]
+; CHECK-NEXT:    [[MAX:%.*]] = fsub nnan <2 x float> <float -0.000000e+00, float -0.000000e+00>, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x float> [[MAX]]
 ;
   %n1 = fsub <2 x float> <float -0.0, float -0.0>, %x
   %n2 = fsub <2 x float> <float -0.0, float -0.0>, %y
   %cond = fcmp nsz nnan uge <2 x float> %n1, %n2
   %max = select <2 x i1> %cond, <2 x float> %n1, <2 x float> %n2
   ret <2 x float> %max
 }

llvm/test/Transforms/InstCombine/pow_fp_int.ll

;
   %pow = tail call afn float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_power_of_2_fast(i31 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_power_of_2_fast(
 ; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i31 [[X:%.*]] to float
-; CHECK-NEXT:    [[MUL:%.*]] = fmul afn float [[SUBFP]], 4.000000e+00
+; CHECK-NEXT:    [[MUL:%.*]] = fmul nnan afn float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call afn float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i31 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
;
   %pow = tail call float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_power_of_2_no_fast(i32 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_power_of_2_no_fast(
 ; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
-; CHECK-NEXT:    [[MUL:%.*]] = fmul float [[SUBFP]], 4.000000e+00
+; CHECK-NEXT:    [[MUL:%.*]] = fmul nnan float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i32 %x to float
   %pow = tail call float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res