PPC: Prepare tests for switch of default denormal-fp-math

[arsenm]

Summary

These tests fail when the default is switched to assume IEEE denormal
handling. I'm not sure if PPC really has a way to control the denormal
input handling.

[steven.zhang]

Sanity check failed with the updated case. (Depending on other patches ?)

llvm/llvm/test/CodeGen/PowerPC/qpx-recipest.ll:320:15: error: CHECK-NEXT: expected string not found in input
; CHECK-NEXT: addis 3, 2, .LCPI12_2@toc@ha
              ^
<stdin>:470:2: note: scanning from here
 qvfmul 0, 0, 1
 ^
<stdin>:470:3: note: possible intended match here
 qvfmul 0, 0, 1

[arsenm]

In D69982#1745637, @steven.zhang wrote:

Sanity check failed with the updated case. (Depending on other patches ?)

llvm/llvm/test/CodeGen/PowerPC/qpx-recipest.ll:320:15: error: CHECK-NEXT: expected string not found in input
; CHECK-NEXT: addis 3, 2, .LCPI12_2@toc@ha
              ^
<stdin>:470:2: note: scanning from here
 qvfmul 0, 0, 1
 ^
<stdin>:470:3: note: possible intended match here
 qvfmul 0, 0, 1

Yes, I added the dependencies

[steven.zhang]

Well, it seems that it is still too early to review this change. One comments: I see that, we have the code sequence change if switch to ieee. sqrt_afn_ieee is slower than sqrt_afn. As you are trying to set it as ieee for target that didn't explicit set the denormal-fp-math, which means that, this will affect PowerPC. Could we have the Frontend set the denormal-fp-math for PowerPC as non-ieee, so that, you don't need this patch any more ?

[arsenm]

In D69982#1746873, @steven.zhang wrote:

Well, it seems that it is still too early to review this change. One comments: I see that, we have the code sequence change if switch to ieee. sqrt_afn_ieee is slower than sqrt_afn. As you are trying to set it as ieee for target that didn't explicit set the denormal-fp-math, which means that, this will affect PowerPC. Could we have the Frontend set the denormal-fp-math for PowerPC as non-ieee, so that, you don't need this patch any more ?

Based on the comments in bug 34994, the current behavior is broken on PowerPC. Denormals are enabled by default, so the sqrt expansion is broken. It would be incorrect to default to non-ieee

[steven.zhang]

Ok, https://reviews.llvm.org/D42323 is the background for this patch. I will leave this to others to continue the review as I am not familiar with floating stuff.

[spatel]

In D69982#1746885, @arsenm wrote:

In D69982#1746873, @steven.zhang wrote:

Well, it seems that it is still too early to review this change. One comments: I see that, we have the code sequence change if switch to ieee. sqrt_afn_ieee is slower than sqrt_afn. As you are trying to set it as ieee for target that didn't explicit set the denormal-fp-math, which means that, this will affect PowerPC. Could we have the Frontend set the denormal-fp-math for PowerPC as non-ieee, so that, you don't need this patch any more ?

Based on the comments in bug 34994, the current behavior is broken on PowerPC. Denormals are enabled by default, so the sqrt expansion is broken. It would be incorrect to default to non-ieee

Bugzilla appears to be dead currently, so I can't check exactly what was written there, but that's what I remember too.
Note that PowerISA rev 2.07 (not sure what current state is) has a bit in the FPSCR that is likely relevant:

Bit 61 - Floating-Point Non-IEEE Mode (NI)
Programming Note:
When the processor is in floating-point non-IEEE mode, the results of floating-point
operations may be approximate, and performance for these operations may be better, 
more predictable, or less data-dependent than when the processor is not in non-IEEE 
mode. For example, in non-IEEE mode an implementation may return 0 instead of a 
denormalized number, and may return a large number instead of an infinity.

I have no idea if/how any recent PPC implementation makes uses of that bit. And I don't know if any compiler sets that bit using tricks (like x86 might).

[arsenm]

ping

[spatel]

LGTM, but someone closer to PPC should approve officially.

llvm/test/CodeGen/PowerPC/qpx-recipest.ll

303

Is the intent to leave this file as-is (no explicit denormal attributes) to show default behavior? Alternatively, we could specify the attribute and decouple this patch from the other patches in this series?

[nemanjai]

This seems straightforward to me - I assume the constant pool load in the test case is some value denoting the smallest normal value for the type. Then rather than comparing against zero do determine when to return zero, we compare against that value (after taking the absolute value).

So if I understand the test case updates correctly, LGTM.

[arsenm]

de716173357f5715fe14788ec022e6eeb2b33540

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn:'
 ; FMFDEBUG:         fmul afn {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn:'
 ; GLOBALDEBUG:         fmul afn {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn:'
 
-define float @sqrt_afn(float %x) {
-; FMF-LABEL: sqrt_afn:
+define float @sqrt_afn_ieee(float %x) #0 {
+; FMF-LABEL: sqrt_afn_ieee:
 ; FMF:       # %bb.0:
+; FMF-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
+; FMF-NEXT:    fabs 0, 1
+; FMF-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
+; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
-; FMF-NEXT:    fcmpu 0, 1, 0
-; FMF-NEXT:    beq 0, .LBB10_2
+; FMF-NEXT:    blt 0, .LBB10_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
 ; FMF-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
 ; FMF-NEXT:    lfs 2, .LCPI10_0@toc@l(3)
 ; FMF-NEXT:    lfs 3, .LCPI10_1@toc@l(4)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:    xsmulsp 1, 1, 2
 ; FMF-NEXT:    xsaddsp 0, 0, 3
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB10_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
-; GLOBAL-LABEL: sqrt_afn:
+; GLOBAL-LABEL: sqrt_afn_ieee:
 ; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
+; GLOBAL-NEXT:    fabs 0, 1
+; GLOBAL-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
+; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
-; GLOBAL-NEXT:    fcmpu 0, 1, 0
-; GLOBAL-NEXT:    beq 0, .LBB10_2
+; GLOBAL-NEXT:    blt 0, .LBB10_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
 ; GLOBAL-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
 ; GLOBAL-NEXT:    lfs 2, .LCPI10_0@toc@l(3)
 ; GLOBAL-NEXT:    lfs 3, .LCPI10_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB10_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call afn float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
+define float @sqrt_afn_preserve_sign(float %x) #1 {
+; FMF-LABEL: sqrt_afn_preserve_sign:
+; FMF:       # %bb.0:
+; FMF-NEXT:    xxlxor 0, 0, 0
+; FMF-NEXT:    fcmpu 0, 1, 0
+; FMF-NEXT:    beq 0, .LBB11_2
+; FMF-NEXT:  # %bb.1:
+; FMF-NEXT:    xsrsqrtesp 0, 1
+; FMF-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
+; FMF-NEXT:    addis 4, 2, .LCPI11_1@toc@ha
+; FMF-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI11_1@toc@l(4)
+; FMF-NEXT:    xsmulsp 1, 1, 0
+; FMF-NEXT:    xsmulsp 0, 1, 0
+; FMF-NEXT:    xsmulsp 1, 1, 2
+; FMF-NEXT:    xsaddsp 0, 0, 3
+; FMF-NEXT:    xsmulsp 0, 1, 0
+; FMF-NEXT:  .LBB11_2:
+; FMF-NEXT:    fmr 1, 0
+; FMF-NEXT:    blr
+;
+; GLOBAL-LABEL: sqrt_afn_preserve_sign:
+; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    xxlxor 0, 0, 0
+; GLOBAL-NEXT:    fcmpu 0, 1, 0
+; GLOBAL-NEXT:    beq 0, .LBB11_2
+; GLOBAL-NEXT:  # %bb.1:
+; GLOBAL-NEXT:    xsrsqrtesp 0, 1
+; GLOBAL-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
+; GLOBAL-NEXT:    addis 4, 2, .LCPI11_1@toc@ha
+; GLOBAL-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI11_1@toc@l(4)
+; GLOBAL-NEXT:    xsmulsp 1, 1, 0
+; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
+; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    xsmulsp 0, 0, 2
+; GLOBAL-NEXT:  .LBB11_2:
+; GLOBAL-NEXT:    fmr 1, 0
+; GLOBAL-NEXT:    blr
+  %rt = call afn float @llvm.sqrt.f32(float %x)
+  ret float %rt
+}
+
 ; The call is now fully 'fast'. This implies that approximation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast:'
 ; FMFDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast:'
 ; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast:'
 
-define float @sqrt_fast(float %x) {
-; FMF-LABEL: sqrt_fast:
+define float @sqrt_fast_ieee(float %x) #0 {
+; FMF-LABEL: sqrt_fast_ieee:
+; FMF:       # %bb.0:
+; FMF-NEXT:    addis 3, 2, .LCPI12_2@toc@ha
+; FMF-NEXT:    fabs 0, 1
+; FMF-NEXT:    lfs 2, .LCPI12_2@toc@l(3)
+; FMF-NEXT:    fcmpu 0, 0, 2
+; FMF-NEXT:    xxlxor 0, 0, 0
+; FMF-NEXT:    blt 0, .LBB12_2
+; FMF-NEXT:  # %bb.1:
+; FMF-NEXT:    xsrsqrtesp 0, 1
+; FMF-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
+; FMF-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
+; FMF-NEXT:    lfs 2, .LCPI12_0@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI12_1@toc@l(4)
+; FMF-NEXT:    xsmulsp 1, 1, 0
+; FMF-NEXT:    xsmaddasp 2, 1, 0
+; FMF-NEXT:    xsmulsp 0, 1, 3
+; FMF-NEXT:    xsmulsp 0, 0, 2
+; FMF-NEXT:  .LBB12_2:
+; FMF-NEXT:    fmr 1, 0
+; FMF-NEXT:    blr
+;
+; GLOBAL-LABEL: sqrt_fast_ieee:
+; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    addis 3, 2, .LCPI12_2@toc@ha
+; GLOBAL-NEXT:    fabs 0, 1
+; GLOBAL-NEXT:    lfs 2, .LCPI12_2@toc@l(3)
+; GLOBAL-NEXT:    fcmpu 0, 0, 2
+; GLOBAL-NEXT:    xxlxor 0, 0, 0
+; GLOBAL-NEXT:    blt 0, .LBB12_2
+; GLOBAL-NEXT:  # %bb.1:
+; GLOBAL-NEXT:    xsrsqrtesp 0, 1
+; GLOBAL-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
+; GLOBAL-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
+; GLOBAL-NEXT:    lfs 2, .LCPI12_0@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI12_1@toc@l(4)
+; GLOBAL-NEXT:    xsmulsp 1, 1, 0
+; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
+; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    xsmulsp 0, 0, 2
+; GLOBAL-NEXT:  .LBB12_2:
+; GLOBAL-NEXT:    fmr 1, 0
+; GLOBAL-NEXT:    blr
+  %rt = call fast float @llvm.sqrt.f32(float %x)
+  ret float %rt
+}
+
+define float @sqrt_fast_preserve_sign(float %x) #1 {
+; FMF-LABEL: sqrt_fast_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    fcmpu 0, 1, 0
-; FMF-NEXT:    beq 0, .LBB11_2
+; FMF-NEXT:    beq 0, .LBB13_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; FMF-NEXT:    addis 4, 2, .LCPI11_1@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
-; FMF-NEXT:    lfs 3, .LCPI11_1@toc@l(4)
+; FMF-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
+; FMF-NEXT:    addis 4, 2, .LCPI13_1@toc@ha
+; FMF-NEXT:    lfs 2, .LCPI13_0@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI13_1@toc@l(4)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
-; FMF-NEXT:  .LBB11_2:
+; FMF-NEXT:  .LBB13_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
-; GLOBAL-LABEL: sqrt_fast:
+; GLOBAL-LABEL: sqrt_fast_preserve_sign:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    fcmpu 0, 1, 0
-; GLOBAL-NEXT:    beq 0, .LBB11_2
+; GLOBAL-NEXT:    beq 0, .LBB13_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; GLOBAL-NEXT:    addis 4, 2, .LCPI11_1@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
-; GLOBAL-NEXT:    lfs 3, .LCPI11_1@toc@l(4)
+; GLOBAL-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
+; GLOBAL-NEXT:    addis 4, 2, .LCPI13_1@toc@ha
+; GLOBAL-NEXT:    lfs 2, .LCPI13_0@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI13_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
-; GLOBAL-NEXT:  .LBB11_2:
+; GLOBAL-NEXT:  .LBB13_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call fast float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; fcmp can have fast-math-flags.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
 ; FMFDEBUG:         select_cc nnan {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fcmp_nnan:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
 ; GLOBALDEBUG:         select_cc nnan {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fcmp_nnan:'
 
 define double @fcmp_nnan(double %a, double %y, double %z) {
 ; FMF-LABEL: fcmp_nnan:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    xscmpudp 0, 1, 0
-; FMF-NEXT:    blt 0, .LBB12_2
+; FMF-NEXT:    blt 0, .LBB14_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    fmr 3, 2
-; FMF-NEXT:  .LBB12_2:
+; FMF-NEXT:  .LBB14_2:
 ; FMF-NEXT:    fmr 1, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fcmp_nnan:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    xscmpudp 0, 1, 0
-; GLOBAL-NEXT:    blt 0, .LBB12_2
+; GLOBAL-NEXT:    blt 0, .LBB14_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    fmr 3, 2
-; GLOBAL-NEXT:  .LBB12_2:
+; GLOBAL-NEXT:  .LBB14_2:
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %cmp = fcmp nnan ult double %a, 0.0
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 }
 
 ; FP library calls can have fast-math-flags.

 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xssubsp 1, 2, 1
 ; GLOBAL-NEXT:    blr
   %neg = fsub float %x, %y
   %add = fsub nsz float 0.0, %neg
   ret float %add
 }
 
+attributes #0 = { "denormal-fp-math"="ieee,ieee" }
+attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" }

llvm/test/CodeGen/PowerPC/qpx-recipest.ll

 ; CHECK-NEXT:    qvgpci 1, 101
 ; CHECK-NEXT:    qvfperm 1, 0, 2, 1
 ; CHECK-NEXT:    blr
 entry:
   %r = fdiv <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x double> @foo3_fmf(<4 x double> %a) nounwind {
 ; CHECK-LABEL: foo3_fmf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; CHECK-NEXT:    qvfrsqrte 0, 1
 ; CHECK-NEXT:    addi 3, 3, .LCPI12_0@toc@l
 ; CHECK-NEXT:    qvlfdx 2, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI12_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI12_1@toc@l
 ; CHECK-NEXT:    qvfmul 3, 0, 0
 ; CHECK-NEXT:    qvfmsub 4, 1, 2, 1
 ; CHECK-NEXT:    qvfnmsub 3, 4, 3, 2
 ; CHECK-NEXT:    qvfmul 0, 0, 3
 ; CHECK-NEXT:    qvfmul 3, 0, 0
 ; CHECK-NEXT:    qvfnmsub 2, 4, 3, 2
 ; CHECK-NEXT:    qvfmul 0, 0, 2
 ; CHECK-NEXT:    qvlfdx 2, 0, 3
+; CHECK-NEXT:    addis 3, 2, .LCPI12_2@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI12_2@toc@l
+; CHECK-NEXT:    qvlfdx 3, 0, 3
 ; CHECK-NEXT:    qvfmul 0, 0, 1
-; CHECK-NEXT:    qvfcmpeq 1, 1, 2
-; CHECK-NEXT:    qvfsel 1, 1, 2, 0
+; CHECK-NEXT:    qvfabs 1, 1
+; CHECK-NEXT:    qvfcmplt 1, 1, 2
+; CHECK-NEXT:    qvfsel 1, 1, 3, 0
 ; CHECK-NEXT:    blr
 entry:
   %r = call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
   ret <4 x double> %r
 }
 
 define <4 x double> @foo3_safe(<4 x double> %a) nounwind {
 ; CHECK-LABEL: foo3_safe:

 ; CHECK-NEXT:    addi 3, 3, .LCPI14_1@toc@l
 ; CHECK-NEXT:    qvlfsx 0, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI14_0@toc@l
 ; CHECK-NEXT:    qvfmuls 4, 2, 2
 ; CHECK-NEXT:    qvfnmsubs 3, 1, 0, 1
 ; CHECK-NEXT:    qvfmadds 0, 3, 4, 0
 ; CHECK-NEXT:    qvlfsx 3, 0, 3
+; CHECK-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI14_2@toc@l
+; CHECK-NEXT:    qvlfsx 4, 0, 3
 ; CHECK-NEXT:    qvfmuls 0, 2, 0
+; CHECK-NEXT:    qvfabs 2, 1
 ; CHECK-NEXT:    qvfmuls 0, 0, 1
-; CHECK-NEXT:    qvfcmpeq 1, 1, 3
-; CHECK-NEXT:    qvfsel 1, 1, 3, 0
+; CHECK-NEXT:    qvfcmplt 1, 2, 3
+; CHECK-NEXT:    qvfsel 1, 1, 4, 0
 ; CHECK-NEXT:    blr
 entry:
   %r = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @goo3_safe(<4 x float> %a) nounwind {
 ; CHECK-LABEL: goo3_safe:

llvm/test/CodeGen/PowerPC/recipest.ll

 define float @goo3_safe(float %a) nounwind {
 ; CHECK: @goo3_safe
 ; CHECK: fsqrts
 ; CHECK: blr
   %r = call float @llvm.sqrt.f32(float %a)
   ret float %r
 }
 
-define <4 x float> @hoo3_fmf(<4 x float> %a) nounwind {
+define <4 x float> @hoo3_fmf(<4 x float> %a) #1 {
 ; CHECK: @hoo3_fmf
 ; CHECK: vrsqrtefp
 ; CHECK-DAG: vcmpeqfp
   %r = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo3_safe(<4 x float> %a) nounwind {
 ; CHECK: @hoo3_safe
 ; CHECK-NOT: vrsqrtefp
 ; CHECK: blr
   %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 attributes #0 = { nounwind "reciprocal-estimates"="sqrtf:0,sqrtd:0" }
+attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }