[amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.

[rampitec]

LGTM

[arsenm]

What was the symptom of this?

llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll

163

Drop the return address register

[hliao]

In D69735#1730811, @arsenm wrote:

What was the symptom of this?

crash as the extra check following that assumes non-zero operands. As all bits are known zero, that results in the conflict finally.

llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll

163

OK

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
   }
   case AMDGPUISD::MUL_U24:
   case AMDGPUISD::MUL_I24: {
     KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
     unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
                       RHSKnown.countMinTrailingZeros();
     Known.Zero.setLowBits(std::min(TrailZ, 32u));
+    // Skip extra check if all bits are known zeros.
+    if (TrailZ >= 32)
+      break;
 
     // Truncate to 24 bits.
     LHSKnown = LHSKnown.trunc(24);
     RHSKnown = RHSKnown.trunc(24);
 
     bool Negative = false;
     if (Opc == AMDGPUISD::MUL_I24) {
       unsigned LHSValBits = 24 - LHSKnown.countMinSignBits();

llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll

; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %w.shl = shl i32 %w, 10
   %w.bits = ashr i32 %w.shl, 10
 
   %mul0 = mul i32 %x.bits, %y.bits
   %mul1 = mul i32 %z.bits, %w.bits
   %mul2 = mul i32 %mul0, %mul1
   ret i32 %mul2
 }
+
+; GFX9-LABEL: known_bits_mul24:
+; GFX9: v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_setpc_b64
+define i32 @known_bits_mul24() {
+  %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7)
+  %r1 = shl i32 %r0, 2
+  ret i32 %r1
+}
+
+declare i32 @llvm.amdgcn.mul.i24(i32, i32)