[Codegen][ARM] Add float softening for cbrt

[dmgreen]

Summary

We would previously have no soft-float softening for cbrt, so could hit a crash failing to select. This fills in what appears to be missing.

[john.brawn]

Would it also make sense to add FCBRT to ExpandFloatResult and PromoteFloatResult? I don't know if it would be possible to test those though.

[dmgreen]

Yeah, adding them is simple enough, but I'm not sure how those might be tested. I have added them here and included a test for halfs (which will not be converted into a cbrt, but if they were may then need promotion).

[efriedma]

LGTM

For promote, you'd need a type with an explicit float specification. "expand" only applies to ppc_f128. So I doubt either case is reachable. But the code is simple enough that the lack of coverage is unlikely to matter.

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

#endif
     case ISD::BUILD_PAIR:  R = SoftenFloatRes_BUILD_PAIR(N); break;
     case ISD::ConstantFP:  R = SoftenFloatRes_ConstantFP(N); break;
     case ISD::EXTRACT_VECTOR_ELT:
       R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
     case ISD::FABS:        R = SoftenFloatRes_FABS(N); break;
     case ISD::FMINNUM:     R = SoftenFloatRes_FMINNUM(N); break;
     case ISD::FMAXNUM:     R = SoftenFloatRes_FMAXNUM(N); break;
     case ISD::FADD:        R = SoftenFloatRes_FADD(N); break;
+    case ISD::FCBRT:       R = SoftenFloatRes_FCBRT(N); break;
     case ISD::FCEIL:       R = SoftenFloatRes_FCEIL(N); break;
     case ISD::FCOPYSIGN:   R = SoftenFloatRes_FCOPYSIGN(N); break;
     case ISD::FCOS:        R = SoftenFloatRes_FCOS(N); break;
     case ISD::FDIV:        R = SoftenFloatRes_FDIV(N); break;
     case ISD::FEXP:        R = SoftenFloatRes_FEXP(N); break;
     case ISD::FEXP2:       R = SoftenFloatRes_FEXP2(N); break;
     case ISD::FFLOOR:      R = SoftenFloatRes_FFLOOR(N); break;
     case ISD::FLOG:        R = SoftenFloatRes_FLOG(N); break;
return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
                                            RTLIB::ADD_F32,
                                            RTLIB::ADD_F64,
                                            RTLIB::ADD_F80,
                                            RTLIB::ADD_F128,
                                            RTLIB::ADD_PPCF128),
                          NVT, Ops, CallOptions, SDLoc(N)).first;
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  SDValue Op = GetSoftenedFloat(N->getOperand(0));
+  TargetLowering::MakeLibCallOptions CallOptions;
+  EVT OpsVT[1] = { N->getOperand(0).getValueType() };
+  CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
+  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
+                                           RTLIB::CBRT_F32,
+                                           RTLIB::CBRT_F64,
+                                           RTLIB::CBRT_F80,
+                                           RTLIB::CBRT_F128,
+                                           RTLIB::CBRT_PPCF128),
+                         NVT, Op, CallOptions, SDLoc(N)).first;
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Op = GetSoftenedFloat(N->getOperand(0));
   TargetLowering::MakeLibCallOptions CallOptions;
   EVT OpsVT[1] = { N->getOperand(0).getValueType() };
   CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
   return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
                                            RTLIB::CEIL_F32,

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue SoftenFloatRes_BITCAST(SDNode *N);
   SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
   SDValue SoftenFloatRes_ConstantFP(SDNode *N);
   SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FABS(SDNode *N);
   SDValue SoftenFloatRes_FMINNUM(SDNode *N);
   SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
   SDValue SoftenFloatRes_FADD(SDNode *N);
+  SDValue SoftenFloatRes_FCBRT(SDNode *N);
   SDValue SoftenFloatRes_FCEIL(SDNode *N);
   SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
   SDValue SoftenFloatRes_FCOS(SDNode *N);
   SDValue SoftenFloatRes_FDIV(SDNode *N);
   SDValue SoftenFloatRes_FEXP(SDNode *N);
   SDValue SoftenFloatRes_FEXP2(SDNode *N);
   SDValue SoftenFloatRes_FFLOOR(SDNode *N);
   SDValue SoftenFloatRes_FLOG(SDNode *N);

llvm/test/CodeGen/ARM/pow.ll

 ; ANY-LABEL: pow_f64_one_fourth_fmf:
 ; SOFTFLOAT:    bl pow
 ; HARDFLOAT:    vsqrt.f64
 ; HARDFLOAT:    vsqrt.f64
   %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01)
   ret double %r
 }
 
+define float @pow_f32_one_third_fmf(float %x) nounwind {
+; ANY-LABEL: pow_f32_one_third_fmf:
+; SOFTFLOAT:    bl cbrtf
+; HARDFLOAT:    b cbrtf
+  %r = call fast float @llvm.pow.f32(float %x, float 0x3FD5555560000000)
+  ret float %r
+}
+
+define double @pow_f64_one_third_fmf(double %x) nounwind {
+; ANY-LABEL: pow_f64_one_third_fmf:
+; SOFTFLOAT:    bl cbrt
+; HARDFLOAT:    b cbrt
+  %r = call fast double @llvm.pow.f64(double %x, double 0x3FD5555555555555)
+  ret double %r
+}
+
 define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind {
 ; ANY-LABEL: pow_v4f32_one_fourth_fmf:
 ; SOFTFLOAT:    bl powf
 ; SOFTFLOAT:    bl powf
 ; SOFTFLOAT:    bl powf
 ; SOFTFLOAT:    bl powf
 ; HARDFLOAT:    vsqrt.f32
 ; HARDFLOAT:    vsqrt.f32