[AMDGPU] Do not combine dpp with physreg def

[rampitec]

Summary

We will remove dpp mov along with the physreg def otherwise.

[arsenm]

LGTM

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

578

Should also add a test with a read of a physreg since that won't work either

[rampitec]

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

578

Right. It still does not work. I will do a separate change.

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

 
 bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
   LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
 
   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
   assert(DstOpnd && DstOpnd->isReg());
   auto DPPMovReg = DstOpnd->getReg();
+  if (DPPMovReg.isPhysical()) {
+    LLVM_DEBUG(dbgs() << "  failed: dpp move writes physreg\n");
+    return false;
+  }
   if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
     LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
                          " for all uses\n");
     return false;
   }
 
   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
   assert(RowMaskOpnd && RowMaskOpnd->isImm());

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

 name: dpp_undef_old
 tracksRegLiveness: true
 body: |
   bb.0:
     %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
 ...
 
+# Do not combine a dpp mov which writes a physreg.
+# GCN-LABEL: name: phys_dpp_mov_dst
+# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
+# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
+name: phys_dpp_mov_dst
+tracksRegLiveness: true
+body: |
+  bb.0:
+    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
+...
+
 # GCN-LABEL: name: dpp_reg_sequence_both_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %9:vgpr_32 = IMPLICIT_DEF
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
 # GCN: %6:vgpr_32 = V_ADD_I32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_both_combined