[llvm-exegesis][NFC] Remove extra `llvm::` qualifications.

[courbet]

Summary

First patch: in unit tests.

[courbet]

Fix build

llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp

 using testing::Not;
 using testing::NotNull;
 
 constexpr const char kTriple[] = "aarch64-unknown-linux";
 
 class AArch64TargetTest : public ::testing::Test {
 protected:
   AArch64TargetTest()
-      : ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) {
+      : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
     EXPECT_THAT(ExegesisTarget_, NotNull());
     std::string error;
-    Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
+    Target_ = TargetRegistry::lookupTarget(kTriple, error);
     EXPECT_THAT(Target_, NotNull());
     STI_.reset(
         Target_->createMCSubtargetInfo(kTriple, "generic", /*no features*/ ""));
   }
 
   static void SetUpTestCase() {
     LLVMInitializeAArch64TargetInfo();
     LLVMInitializeAArch64Target();
     LLVMInitializeAArch64TargetMC();
     InitializeAArch64ExegesisTarget();
   }
 
   std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
     return ExegesisTarget_->setRegTo(*STI_, Reg, Value);
   }
 
-  const llvm::Target *Target_;
+  const Target *Target_;
   const ExegesisTarget *const ExegesisTarget_;
-  std::unique_ptr<llvm::MCSubtargetInfo> STI_;
+  std::unique_ptr<MCSubtargetInfo> STI_;
 };
 
 TEST_F(AArch64TargetTest, SetRegToConstant) {
   // The AArch64 target currently doesn't know how to set register values.
-  const auto Insts = setRegTo(llvm::AArch64::X0, llvm::APInt());
+  const auto Insts = setRegTo(AArch64::X0, APInt());
   EXPECT_THAT(Insts, Not(IsEmpty()));
 }
 
 TEST_F(AArch64TargetTest, DefaultPfmCounters) {
   const std::string Expected = "CPU_CYCLES";
   EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, Expected);
   EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
             Expected);
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp

 //===-- AssemblerTest.cpp ---------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "../Common/AssemblerUtils.h"
 #include "ARMInstrInfo.h"
 
 namespace llvm {
 namespace exegesis {
 namespace {
 
-using llvm::MCInstBuilder;
-
 class ARMMachineFunctionGeneratorTest
     : public MachineFunctionGeneratorBaseTest {
 protected:
   ARMMachineFunctionGeneratorTest()
       : MachineFunctionGeneratorBaseTest("armv7-none-linux-gnueabi", "") {}
 
   static void SetUpTestCase() {
     LLVMInitializeARMTargetInfo();
     LLVMInitializeARMTargetMC();
     LLVMInitializeARMTarget();
     LLVMInitializeARMAsmPrinter();
   }
 };
 
 TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunction) {
-  Check({}, llvm::MCInst(), 0x1e, 0xff, 0x2f, 0xe1);
+  Check({}, MCInst(), 0x1e, 0xff, 0x2f, 0xe1);
 }
 
 TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunctionADDrr) {
-  Check({{llvm::ARM::R0, llvm::APInt()}},
-        MCInstBuilder(llvm::ARM::ADDrr)
-            .addReg(llvm::ARM::R0)
-            .addReg(llvm::ARM::R0)
-            .addReg(llvm::ARM::R0)
-            .addImm(llvm::ARMCC::AL)
+  Check({{ARM::R0, APInt()}},
+        MCInstBuilder(ARM::ADDrr)
+            .addReg(ARM::R0)
+            .addReg(ARM::R0)
+            .addReg(ARM::R0)
+            .addImm(ARMCC::AL)
             .addReg(0)
             .addReg(0),
         0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1);
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h

 namespace llvm {
 namespace exegesis {
 
 class MachineFunctionGeneratorBaseTest : public ::testing::Test {
 protected:
   MachineFunctionGeneratorBaseTest(const std::string &TT,
                                    const std::string &CpuName)
       : TT(TT), CpuName(CpuName),
-        CanExecute(llvm::Triple(TT).getArch() ==
-                   llvm::Triple(llvm::sys::getProcessTriple()).getArch()),
-        ET(ExegesisTarget::lookup(llvm::Triple(TT))) {
+        CanExecute(Triple(TT).getArch() ==
+                   Triple(sys::getProcessTriple()).getArch()),
+        ET(ExegesisTarget::lookup(Triple(TT))) {
     assert(ET);
     if (!CanExecute) {
-      llvm::outs() << "Skipping execution, host:"
-                   << llvm::sys::getProcessTriple() << ", target:" << TT
-                   << "\n";
+      outs() << "Skipping execution, host:" << sys::getProcessTriple()
+             << ", target:" << TT << "\n";
     }
   }
 
   template <class... Bs>
   inline void Check(ArrayRef<RegisterValue> RegisterInitialValues, MCInst Inst,
                     Bs... Bytes) {
     ExecutableFunction Function =
         (Inst.getOpcode() == 0)
             ? assembleToFunction(RegisterInitialValues, [](FunctionFiller &) {})
             : assembleToFunction(RegisterInitialValues,
                                  [Inst](FunctionFiller &Filler) {
                                    Filler.getEntry().addInstruction(Inst);
                                  });
     ASSERT_THAT(Function.getFunctionBytes().str(),
                 testing::ElementsAre(Bytes...));
     if (CanExecute) {
       BenchmarkRunner::ScratchSpace Scratch;
       Function(Scratch.ptr());
     }
   }
 
 private:
-  std::unique_ptr<llvm::LLVMTargetMachine> createTargetMachine() {
+  std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
     std::string Error;
-    const llvm::Target *TheTarget =
-        llvm::TargetRegistry::lookupTarget(TT, Error);
+    const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
     EXPECT_TRUE(TheTarget) << Error << " " << TT;
-    const llvm::TargetOptions Options;
-    llvm::TargetMachine *TM = TheTarget->createTargetMachine(
-        TT, CpuName, "", Options, llvm::Reloc::Model::Static);
+    const TargetOptions Options;
+    TargetMachine *TM = TheTarget->createTargetMachine(TT, CpuName, "", Options,
+                                                       Reloc::Model::Static);
     EXPECT_TRUE(TM) << TT << " " << CpuName;
-    return std::unique_ptr<llvm::LLVMTargetMachine>(
-        static_cast<llvm::LLVMTargetMachine *>(TM));
+    return std::unique_ptr<LLVMTargetMachine>(
+        static_cast<LLVMTargetMachine *>(TM));
   }
 
   ExecutableFunction
-  assembleToFunction(llvm::ArrayRef<RegisterValue> RegisterInitialValues,
+  assembleToFunction(ArrayRef<RegisterValue> RegisterInitialValues,
                      FillFunction Fill) {
-    llvm::SmallString<256> Buffer;
-    llvm::raw_svector_ostream AsmStream(Buffer);
+    SmallString<256> Buffer;
+    raw_svector_ostream AsmStream(Buffer);
     assembleToStream(*ET, createTargetMachine(), /*LiveIns=*/{},
                      RegisterInitialValues, Fill, AsmStream);
     return ExecutableFunction(createTargetMachine(),
                               getObjectFromBuffer(AsmStream.str()));
   }
 
   const std::string TT;
   const std::string CpuName;
   const bool CanExecute;
   const ExegesisTarget *const ET;
 };
 
 } // namespace exegesis
 } // namespace llvm
 
 #endif

llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp

 TEST(PerfHelperTest, FunctionalTest) {
 #ifdef HAVE_LIBPFM
   ASSERT_FALSE(pfmInitialize());
   const PerfEvent SingleEvent("CYCLES:u");
   const auto &EmptyFn = []() {};
   std::string CallbackEventName;
   std::string CallbackEventNameFullyQualifed;
   int64_t CallbackEventCycles;
-  Measure(llvm::makeArrayRef(SingleEvent),
-          [&](const PerfEvent &Event, int64_t Value) {
-            CallbackEventName = Event.name();
-            CallbackEventNameFullyQualifed = Event.getPfmEventString();
-            CallbackEventCycles = Value;
-          },
-          EmptyFn);
+  Measure(
+      makeArrayRef(SingleEvent),
   EXPECT_EQ(CallbackEventName, "CYCLES:u");
   EXPECT_THAT(CallbackEventNameFullyQualifed, Not(IsEmpty()));
   pfmTerminate();
 #else
   ASSERT_TRUE(pfmInitialize());
 #endif
 }
 
 } // namespace
 } // namespace pfm
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp

 using testing::Pair;
 using testing::UnorderedElementsAre;
 
 class AnalysisTest : public ::testing::Test {
 protected:
   AnalysisTest() {
     const std::string TT = "powerpc64le-unknown-linux";
     std::string error;
-    const llvm::Target *const TheTarget =
-        llvm::TargetRegistry::lookupTarget(TT, error);
+    const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error);
     if (!TheTarget) {
-      llvm::errs() << error << "\n";
+      errs() << error << "\n";
       return;
     }
     STI.reset(TheTarget->createMCSubtargetInfo(TT, "pwr9", ""));
 
     // Compute the ProxResIdx of ports uses in tests.
     const auto &SM = STI->getSchedModel();
     for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
       const std::string Name = SM.getProcResource(I)->Name;
protected:
 
   static void SetUpTestCase() {
     LLVMInitializePowerPCTargetInfo();
     LLVMInitializePowerPCTarget();
     LLVMInitializePowerPCTargetMC();
   }
 
 protected:
-  std::unique_ptr<const llvm::MCSubtargetInfo> STI;
+  std::unique_ptr<const MCSubtargetInfo> STI;
   uint16_t ALUIdx = 0;
   uint16_t ALUEIdx = 0;
   uint16_t ALUOIdx = 0;
   uint16_t IPAGENIdx = 0;
 };
 
 TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2ALU) {
   const auto Pressure =

llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp

 using testing::IsEmpty;
 using testing::Not;
 
 constexpr const char kTriple[] = "powerpc64le-unknown-linux";
 
 class PowerPCTargetTest : public ::testing::Test {
 protected:
   PowerPCTargetTest()
-      : ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) {
+      : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
     EXPECT_THAT(ExegesisTarget_, NotNull());
     std::string error;
-    Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
+    Target_ = TargetRegistry::lookupTarget(kTriple, error);
     EXPECT_THAT(Target_, NotNull());
   }
   static void SetUpTestCase() {
     LLVMInitializePowerPCTargetInfo();
     LLVMInitializePowerPCTarget();
     LLVMInitializePowerPCTargetMC();
     InitializePowerPCExegesisTarget();
   }
 
-  const llvm::Target *Target_;
+  const Target *Target_;
   const ExegesisTarget *const ExegesisTarget_;
 };
 
 TEST_F(PowerPCTargetTest, SetRegToConstant) {
-  const std::unique_ptr<llvm::MCSubtargetInfo> STI(
+  const std::unique_ptr<MCSubtargetInfo> STI(
       Target_->createMCSubtargetInfo(kTriple, "generic", ""));
-  const auto Insts =
-      ExegesisTarget_->setRegTo(*STI, llvm::PPC::X0, llvm::APInt());
+  const auto Insts = ExegesisTarget_->setRegTo(*STI, PPC::X0, APInt());
   EXPECT_THAT(Insts, Not(IsEmpty()));
 }
 
 TEST_F(PowerPCTargetTest, DefaultPfmCounters) {
   const std::string Expected = "CYCLES";
   EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, Expected);
   EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
             Expected);
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp

 #include "gtest/gtest.h"
 
 namespace llvm {
 namespace exegesis {
 
 namespace {
 
 #define CHECK(EXPECTED, ACTUAL)                                                \
-  EXPECT_EQ(llvm::APInt(SizeInBits, EXPECTED, 16),                             \
+  EXPECT_EQ(APInt(SizeInBits, EXPECTED, 16),                                   \
             bitcastFloatValue(Semantic, PredefinedValues::ACTUAL))
 
 TEST(RegisterValueTest, Half) {
   const size_t SizeInBits = 16;
-  const auto &Semantic = llvm::APFloatBase::IEEEhalf();
+  const auto &Semantic = APFloatBase::IEEEhalf();
   CHECK("0000", POS_ZERO);
   CHECK("8000", NEG_ZERO);
   CHECK("3C00", ONE);
   CHECK("4000", TWO);
   CHECK("7C00", INF);
   CHECK("7E00", QNAN);
   CHECK("7BFF", LARGEST);
   CHECK("0400", SMALLEST_NORM);
   CHECK("0001", SMALLEST);
   CHECK("0001", ULP);
   CHECK("3C01", ONE_PLUS_ULP);
 }
 
 TEST(RegisterValueTest, Single) {
   const size_t SizeInBits = 32;
-  const auto &Semantic = llvm::APFloatBase::IEEEsingle();
+  const auto &Semantic = APFloatBase::IEEEsingle();
   CHECK("00000000", POS_ZERO);
   CHECK("80000000", NEG_ZERO);
   CHECK("3F800000", ONE);
   CHECK("40000000", TWO);
   CHECK("7F800000", INF);
   CHECK("7FC00000", QNAN);
   CHECK("7F7FFFFF", LARGEST);
   CHECK("00800000", SMALLEST_NORM);
   CHECK("00000001", SMALLEST);
   CHECK("00000001", ULP);
   CHECK("3F800001", ONE_PLUS_ULP);
 }
 
 TEST(RegisterValueTest, Double) {
   const size_t SizeInBits = 64;
-  const auto &Semantic = llvm::APFloatBase::IEEEdouble();
+  const auto &Semantic = APFloatBase::IEEEdouble();
   CHECK("0000000000000000", POS_ZERO);
   CHECK("8000000000000000", NEG_ZERO);
   CHECK("3FF0000000000000", ONE);
   CHECK("4000000000000000", TWO);
   CHECK("7FF0000000000000", INF);
   CHECK("7FF8000000000000", QNAN);
   CHECK("7FEFFFFFFFFFFFFF", LARGEST);
   CHECK("0010000000000000", SMALLEST_NORM);
   CHECK("0000000000000001", SMALLEST);
   CHECK("0000000000000001", ULP);
   CHECK("3FF0000000000001", ONE_PLUS_ULP);
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp

static void SetUpTestCase() {
     LLVMInitializeX86TargetMC();
     LLVMInitializeX86Target();
     LLVMInitializeX86AsmPrinter();
     InitializeX86ExegesisTarget();
   }
 };
 
 TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunction) {
-  Check({}, llvm::MCInst(), 0xc3);
+  Check({}, MCInst(), 0xc3);
 }
 
 TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr_X86) {
-  Check({{EAX, llvm::APInt(32, 1)}},
+  Check({{EAX, APInt(32, 1)}},
         MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
         // mov eax, 1
         0xb8, 0x01, 0x00, 0x00, 0x00,
         // xor eax, eax
         0x31, 0xc0, 0xc3);
 }
 
 TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV64ri) {

llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp

 namespace llvm {
 namespace exegesis {
 
 bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) {
   return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) ==
          std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue);
 }
 
-static std::string Dump(const llvm::MCInst &McInst) {
+static std::string Dump(const MCInst &McInst) {
   std::string Buffer;
-  llvm::raw_string_ostream OS(Buffer);
+  raw_string_ostream OS(Buffer);
   McInst.print(OS);
   return Buffer;
 }
 
 MATCHER(EqMCInst, "") {
   const std::string Lhs = Dump(get<0>(arg));
   const std::string Rhs = Dump(get<1>(arg));
   if (Lhs != Rhs) {
     *result_listener << Lhs << " <=> " << Rhs;
     return false;
   }
   return true;
 }
 
 namespace {
 
 TEST(BenchmarkResultTest, WriteToAndReadFromDisk) {
   LLVMInitializeX86TargetInfo();
   LLVMInitializeX86Target();
   LLVMInitializeX86TargetMC();
 
   // Read benchmarks.
   const LLVMState State("x86_64-unknown-linux", "haswell");
 
-  llvm::ExitOnError ExitOnErr;
+  ExitOnError ExitOnErr;
 
   InstructionBenchmark ToDisk;
 
-  ToDisk.Key.Instructions.push_back(llvm::MCInstBuilder(llvm::X86::XOR32rr)
-                                        .addReg(llvm::X86::AL)
-                                        .addReg(llvm::X86::AH)
+  ToDisk.Key.Instructions.push_back(MCInstBuilder(X86::XOR32rr)
+                                        .addReg(X86::AL)
+                                        .addReg(X86::AH)
                                         .addImm(123)
                                         .addFPImm(0.5));
   ToDisk.Key.Config = "config";
   ToDisk.Key.RegisterInitialValues = {
-      RegisterValue{llvm::X86::AL, llvm::APInt(8, "-1", 10)},
-      RegisterValue{llvm::X86::AH, llvm::APInt(8, "123", 10)}};
+      RegisterValue{X86::AL, APInt(8, "-1", 10)},
+      RegisterValue{X86::AH, APInt(8, "123", 10)}};
   ToDisk.Mode = InstructionBenchmark::Latency;
   ToDisk.CpuName = "cpu_name";
   ToDisk.LLVMTriple = "llvm_triple";
   ToDisk.NumRepetitions = 1;
   ToDisk.Measurements.push_back(BenchmarkMeasure{"a", 1, 1});
   ToDisk.Measurements.push_back(BenchmarkMeasure{"b", 2, 2});
   ToDisk.Error = "error";
   ToDisk.Info = "info";
 
-  llvm::SmallString<64> Filename;
+  SmallString<64> Filename;
   std::error_code EC;
-  EC = llvm::sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename);
+  EC = sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename);
   ASSERT_FALSE(EC);
-  llvm::sys::path::append(Filename, "data.yaml");
-  llvm::errs() << Filename << "-------\n";
+  sys::path::append(Filename, "data.yaml");
+  errs() << Filename << "-------\n";
   ExitOnErr(ToDisk.writeYaml(State, Filename));
 
   {
     // One-element version.
     const auto FromDisk =
         ExitOnErr(InstructionBenchmark::readYaml(State, Filename));
 
     EXPECT_THAT(FromDisk.Key.Instructions,

llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp

 namespace llvm {
 namespace exegesis {
 namespace {
 
 class RegisterAliasingTest : public X86TestBase {};
 
 TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
   const auto &RegInfo = State.getRegInfo();
-  const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX);
-  std::set<llvm::MCPhysReg> ActualAliasedRegisters;
+  const RegisterAliasingTracker tracker(RegInfo, X86::EAX);
+  std::set<MCPhysReg> ActualAliasedRegisters;
   for (unsigned I : tracker.aliasedBits().set_bits())
-    ActualAliasedRegisters.insert(static_cast<llvm::MCPhysReg>(I));
-  const std::set<llvm::MCPhysReg> ExpectedAliasedRegisters = {
-      llvm::X86::AL,  llvm::X86::AH,  llvm::X86::AX,
-      llvm::X86::EAX, llvm::X86::HAX, llvm::X86::RAX};
+    ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
+  const std::set<MCPhysReg> ExpectedAliasedRegisters = {
+      X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
   ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
-  for (llvm::MCPhysReg aliased : ExpectedAliasedRegisters) {
-    ASSERT_THAT(tracker.getOrigin(aliased), llvm::X86::EAX);
+  for (MCPhysReg aliased : ExpectedAliasedRegisters) {
+    ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX);
   }
 }
 
 TEST_F(RegisterAliasingTest, TrackRegisterClass) {
   // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
   // AL, BL, CL and DL.
   const auto &RegInfo = State.getRegInfo();
-  const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
+  const BitVector NoReservedReg(RegInfo.getNumRegs());
 
   const RegisterAliasingTracker RegClassTracker(
-      RegInfo, NoReservedReg,
-      RegInfo.getRegClass(llvm::X86::GR8_ABCD_LRegClassID));
+      RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID));
 
-  llvm::BitVector sum(RegInfo.getNumRegs());
-  sum |= RegisterAliasingTracker(RegInfo, llvm::X86::AL).aliasedBits();
-  sum |= RegisterAliasingTracker(RegInfo, llvm::X86::BL).aliasedBits();
-  sum |= RegisterAliasingTracker(RegInfo, llvm::X86::CL).aliasedBits();
-  sum |= RegisterAliasingTracker(RegInfo, llvm::X86::DL).aliasedBits();
+  BitVector sum(RegInfo.getNumRegs());
+  sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits();
+  sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits();
+  sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits();
+  sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits();
 
   ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
 }
 
 TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
   // Fetching twice the same tracker yields the same pointers.
   const auto &RegInfo = State.getRegInfo();
-  const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
+  const BitVector NoReservedReg(RegInfo.getNumRegs());
   RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
-  ASSERT_THAT(&Cache.getRegister(llvm::X86::AX),
-              &Cache.getRegister(llvm::X86::AX));
+  ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));
 
-  ASSERT_THAT(&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID),
-              &Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID));
+  ASSERT_THAT(&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID),
+              &Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp

SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
     EXPECT_NE(P1Idx, 0);
     EXPECT_NE(P5Idx, 0);
     EXPECT_NE(P6Idx, 0);
     EXPECT_NE(P05Idx, 0);
     EXPECT_NE(P0156Idx, 0);
   }
 
 protected:
-  const llvm::MCSubtargetInfo &STI;
+  const MCSubtargetInfo &STI;
   uint16_t P0Idx = 0;
   uint16_t P1Idx = 0;
   uint16_t P5Idx = 0;
   uint16_t P6Idx = 0;
   uint16_t P05Idx = 0;
   uint16_t P0156Idx = 0;
 };
 

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
 
 class X86SnippetGeneratorTest : public X86TestBase {
 protected:
   X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {}
 
-  const llvm::MCInstrInfo &InstrInfo;
+  const MCInstrInfo &InstrInfo;
 };
 
 template <typename SnippetGeneratorT>
 class SnippetGeneratorTest : public X86SnippetGeneratorTest {
 protected:
   SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
 
   std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
   // - Op0 Explicit Use Immediate
   // - Op1 Implicit Def Reg(AX)
   // - Op2 Implicit Def Reg(EFLAGS)
   // - Op3 Implicit Use Reg(AX)
   // - Op4 Implicit Use Reg(EFLAGS)
   // - Var0 [Op0]
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::ADC16i16;
-  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
-  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
-  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
-  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
+  const unsigned Opcode = X86::ADC16i16;
+  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
+  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS);
+  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
+  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.VariableValues, SizeIs(1)); // Imm.
   EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
   // - ADD16ri
   // - Op0 Explicit Def RegClass(GR16)
   // - Op1 Explicit Use RegClass(GR16) TiedToOp0
   // - Op2 Explicit Use Immediate
   // - Op3 Implicit Def Reg(EFLAGS)
   // - Var0 [Op0,Op1]
   // - Var1 [Op2]
   // - hasTiedRegisters (execution is always serial)
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::ADD16ri;
-  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
+  const unsigned Opcode = X86::ADD16ri;
+  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.VariableValues, SizeIs(2));
   EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
   EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - VXORPSrr
   // - Op0 Explicit Def RegClass(VR128)
   // - Op1 Explicit Use RegClass(VR128)
   // - Op2 Explicit Use RegClass(VR128)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::VXORPSrr;
+  const unsigned Opcode = X86::VXORPSrr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.VariableValues, SizeIs(3));
   EXPECT_THAT(IT.VariableValues,
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
 TEST_F(LatencySnippetGeneratorTest,
        ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - VXORPSrr
   // - Op0 Explicit Def RegClass(VR128)
   // - Op1 Explicit Use RegClass(VR128)
   // - Op2 Explicit Use RegClass(VR128)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::VXORPSrr;
+  const unsigned Opcode = X86::VXORPSrr;
   randomGenerator().seed(0); // Initialize seed.
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   auto AllRegisters = State.getRATC().emptyRegisters();
   AllRegisters.flip();
   auto Error = Generator.generateCodeTemplates(Instr, AllRegisters).takeError();
   EXPECT_TRUE((bool)Error);
-  llvm::consumeError(std::move(Error));
+  consumeError(std::move(Error));
 }
 
 TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
   // - CMP64rr
   // - Op0 Explicit Use RegClass(GR64)
   // - Op1 Explicit Use RegClass(GR64)
   // - Op2 Implicit Def Reg(EFLAGS)
   // - Var0 [Op0]
   // - Var1 [Op1]
-  const unsigned Opcode = llvm::X86::CMP64rr;
+  const unsigned Opcode = X86::CMP64rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
     ASSERT_THAT(IT.VariableValues, SizeIs(2));
     EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
                                          ElementsAre(IsInvalid(), IsReg())));
     EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
     // TODO: check that the two instructions alias each other.
   }
 }
 
 TEST_F(LatencySnippetGeneratorTest, LAHF) {
   // - LAHF
   // - Op0 Implicit Def Reg(AH)
   // - Op1 Implicit Use Reg(EFLAGS)
-  const unsigned Opcode = llvm::X86::LAHF;
+  const unsigned Opcode = X86::LAHF;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
     ASSERT_THAT(IT.VariableValues, SizeIs(0));
   }
 }
 
 TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
   // - BNDCL32rr
   // - Op0 Explicit Use RegClass(BNDR)
   // - Op1 Explicit Use RegClass(GR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
-  const unsigned Opcode = llvm::X86::BNDCL32rr;
+  const unsigned Opcode = X86::BNDCL32rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("parallel"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.VariableValues, SizeIs(2));
   EXPECT_THAT(IT.VariableValues[0], IsInvalid());
   EXPECT_THAT(IT.VariableValues[1], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
   // - CDQ
   // - Op0 Implicit Def Reg(EAX)
   // - Op1 Implicit Def Reg(EDX)
   // - Op2 Implicit Use Reg(EAX)
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::CDQ;
+  const unsigned Opcode = X86::CDQ;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("serial"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
   // - Op1 Explicit Use RegClass(GR32) TiedToOp0
   // - Op2 Explicit Use RegClass(GR32)
   // - Op3 Explicit Use Immediate
   // - Op3 Implicit Use Reg(EFLAGS)
   // - Var0 [Op0,Op1]
   // - Var1 [Op2]
   // - hasTiedRegisters (execution is always serial)
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::CMOV32rr;
+  const unsigned Opcode = X86::CMOV32rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   constexpr const unsigned kInstructionCount = 15;
   ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   // - Op2 Explicit Use RegClass(GR32)
   // - Op3 Explicit Use Immediate
   // - Op4 Implicit Use Reg(EFLAGS)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - Var3 [Op3]
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::CMOV_GR32;
+  const unsigned Opcode = X86::CMOV_GR32;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - Var3 [Op3]
   // - Var4 [Op4]
   // - Var5 [Op5]
   // - hasMemoryOperands
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::MOV32rm;
+  const unsigned Opcode = X86::MOV32rm;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions,
               SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
   const InstructionTemplate &IT = CT.Instructions[0];
public:
   FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
       : SnippetGenerator(State, Opts) {}
 
   Instruction createInstruction(unsigned Opcode) {
     return State.getIC().getInstr(Opcode);
   }
 
 private:
-  llvm::Expected<std::vector<CodeTemplate>>
+  Expected<std::vector<CodeTemplate>>
   generateCodeTemplates(const Instruction &, const BitVector &) const override {
-    return llvm::make_error<llvm::StringError>("not implemented",
-                                               llvm::inconvertibleErrorCode());
+    return make_error<StringError>("not implemented", inconvertibleErrorCode());
   }
 };
 
 using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;
 
 testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
-                                                        llvm::APInt Value) {
+                                                        APInt Value) {
   return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
                         testing::Field(&RegisterValue::Value, Value));
 }
 
 TEST_F(FakeSnippetGeneratorTest, MemoryUse_Movsb) {
   // MOVSB writes to scratch memory register.
   // - MOVSB
   // - Op0 Explicit Use Memory RegClass(GR8)
   // - Op1 Explicit Use Memory RegClass(GR8)
   // - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
   // - Op3 Implicit Def Reg(EDI)
   // - Op4 Implicit Def Reg(ESI)
   // - Op5 Implicit Use Reg(EDI)
   // - Op6 Implicit Use Reg(ESI)
   // - Op7 Implicit Use Reg(DF)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasMemoryOperands
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
-  const unsigned Opcode = llvm::X86::MOVSB;
+  const unsigned Opcode = X86::MOVSB;
   const Instruction &Instr = State.getIC().getInstr(Opcode);
   auto Error =
       Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters())
           .takeError();
   EXPECT_TRUE((bool)Error);
-  llvm::consumeError(std::move(Error));
+  consumeError(std::move(Error));
 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
   // ADD16ri:
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
-  InstructionTemplate IT(Generator.createInstruction(llvm::X86::ADD16ri));
-  IT.getValueFor(IT.Instr.Variables[0]) =
-      llvm::MCOperand::createReg(llvm::X86::AX);
+  InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri));
+  IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
   std::vector<InstructionTemplate> Snippet;
   Snippet.push_back(std::move(IT));
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
-  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::AX, llvm::APInt())));
+  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
   // -> only rbx needs defining.
   std::vector<InstructionTemplate> Snippet;
   {
-    InstructionTemplate Mov(Generator.createInstruction(llvm::X86::MOV64ri));
-    Mov.getValueFor(Mov.Instr.Variables[0]) =
-        llvm::MCOperand::createReg(llvm::X86::RAX);
-    Mov.getValueFor(Mov.Instr.Variables[1]) = llvm::MCOperand::createImm(42);
+    InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri));
+    Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
+    Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42);
     Snippet.push_back(std::move(Mov));
   }
   {
-    InstructionTemplate Add(Generator.createInstruction(llvm::X86::ADD64rr));
-    Add.getValueFor(Add.Instr.Variables[0]) =
-        llvm::MCOperand::createReg(llvm::X86::RAX);
-    Add.getValueFor(Add.Instr.Variables[1]) =
-        llvm::MCOperand::createReg(llvm::X86::RBX);
+    InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));
+    Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
+    Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX);
     Snippet.push_back(std::move(Add));
   }
 
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
-  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::RBX, llvm::APInt())));
+  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

 
 Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
   return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg), IsImm(Value)));
 }
 
 Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
                                   size_t Offset) {
   return AllOf(OpcodeIs(Opcode),
-               ElementsAre(IsReg(llvm::X86::RSP), IsImm(1), IsReg(0),
-                           IsImm(Offset), IsReg(0), IsImm(Value)));
+               ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset),
+                           IsReg(0), IsImm(Value)));
 }
 
 Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {
   return AllOf(OpcodeIs(Opcode),
-               ElementsAre(IsReg(Reg), IsReg(llvm::X86::RSP), IsImm(1),
-                           IsReg(0), IsImm(0), IsReg(0)));
+               ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0),
+                           IsImm(0), IsReg(0)));
 }
 
 Matcher<MCInst> IsStackAllocate(unsigned Size) {
-  return AllOf(
-      OpcodeIs(llvm::X86::SUB64ri8),
-      ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size)));
+  return AllOf(OpcodeIs(X86::SUB64ri8),
+               ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
 }
 
 Matcher<MCInst> IsStackDeallocate(unsigned Size) {
-  return AllOf(
-      OpcodeIs(llvm::X86::ADD64ri8),
-      ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size)));
+  return AllOf(OpcodeIs(X86::ADD64ri8),
+               ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
 }
 
 constexpr const char kTriple[] = "x86_64-unknown-linux";
 
 class X86TargetTest : public ::testing::Test {
 protected:
   X86TargetTest(const char *Features) : State(kTriple, "core2", Features) {}
 
public:
   Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
 };
 
 TEST_F(Core2TargetTest, NoHighByteRegs) {
   EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
 }
 
 TEST_F(Core2TargetTest, SetFlags) {
-  const unsigned Reg = llvm::X86::EFLAGS;
-  EXPECT_THAT(
-      setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
+  const unsigned Reg = X86::EFLAGS;
+  EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(8),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
-                  OpcodeIs(llvm::X86::POPF64)));
+                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
+                          OpcodeIs(X86::POPF64)));
 }
 
 TEST_F(Core2TargetTest, SetRegToGR8Value) {
   const uint8_t Value = 0xFFU;
-  const unsigned Reg = llvm::X86::AL;
+  const unsigned Reg = X86::AL;
   EXPECT_THAT(setRegTo(Reg, APInt(8, Value)),
-              ElementsAre(IsMovImmediate(llvm::X86::MOV8ri, Reg, Value)));
+              ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value)));
 }
 
 TEST_F(Core2TargetTest, SetRegToGR16Value) {
   const uint16_t Value = 0xFFFFU;
-  const unsigned Reg = llvm::X86::BX;
+  const unsigned Reg = X86::BX;
   EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
-              ElementsAre(IsMovImmediate(llvm::X86::MOV16ri, Reg, Value)));
+              ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value)));
 }
 
 TEST_F(Core2TargetTest, SetRegToGR32Value) {
   const uint32_t Value = 0x7FFFFU;
-  const unsigned Reg = llvm::X86::ECX;
+  const unsigned Reg = X86::ECX;
   EXPECT_THAT(setRegTo(Reg, APInt(32, Value)),
-              ElementsAre(IsMovImmediate(llvm::X86::MOV32ri, Reg, Value)));
+              ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value)));
 }
 
 TEST_F(Core2TargetTest, SetRegToGR64Value) {
   const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL;
-  const unsigned Reg = llvm::X86::RDX;
+  const unsigned Reg = X86::RDX;
   EXPECT_THAT(setRegTo(Reg, APInt(64, Value)),
-              ElementsAre(IsMovImmediate(llvm::X86::MOV64ri, Reg, Value)));
+              ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value)));
 }
 
 TEST_F(Core2TargetTest, SetRegToVR64Value) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::MM0, APInt(64, 0x1111222233334444ULL)),
+  EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(8),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
-                  IsMovValueFromStack(llvm::X86::MMX_MOVQ64rm, llvm::X86::MM0),
+                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
+                          IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0),
                           IsStackDeallocate(8)));
 }
 
 TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
   EXPECT_THAT(
-      setRegTo(llvm::X86::XMM0,
-               APInt(128, "11112222333344445555666677778888", 16)),
+      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
       ElementsAre(IsStackAllocate(16),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
-                  IsMovValueFromStack(llvm::X86::MOVDQUrm, llvm::X86::XMM0),
+                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
+                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
+                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
+                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
+                  IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
 TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
   EXPECT_THAT(
-      setRegTo(llvm::X86::XMM0,
-               APInt(128, "11112222333344445555666677778888", 16)),
+      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
       ElementsAre(IsStackAllocate(16),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
-                  IsMovValueFromStack(llvm::X86::VMOVDQUrm, llvm::X86::XMM0),
+                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
+                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
+                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
+                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
+                  IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
 TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
   EXPECT_THAT(
-      setRegTo(llvm::X86::XMM0,
-               APInt(128, "11112222333344445555666677778888", 16)),
-      ElementsAre(
-          IsStackAllocate(16),
-          IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0),
-          IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4),
-          IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8),
-          IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12),
-          IsMovValueFromStack(llvm::X86::VMOVDQU32Z128rm, llvm::X86::XMM0),
+      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
+      ElementsAre(IsStackAllocate(16),
+                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
+                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
+                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
+                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
+                  IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0),
                   IsStackDeallocate(16)));
 }
 
 TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888";
-  EXPECT_THAT(setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)),
-              ElementsAreArray(
-                  {IsStackAllocate(32),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24),
-                   IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28),
-                   IsMovValueFromStack(llvm::X86::VMOVDQUYrm, llvm::X86::YMM0),
+  EXPECT_THAT(
+      setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
+      ElementsAreArray({IsStackAllocate(32),
+                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
+                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
+                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
+                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
+                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
+                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
+                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
+                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
+                        IsMovValueFromStack(X86::VMOVDQUYrm, X86::YMM0),
                         IsStackDeallocate(32)}));
 }
 
 TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888";
   EXPECT_THAT(
-      setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)),
-      ElementsAreArray(
-          {IsStackAllocate(32),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28),
-           IsMovValueFromStack(llvm::X86::VMOVDQU32Z256rm, llvm::X86::YMM0),
+      setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
+      ElementsAreArray({IsStackAllocate(32),
+                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
+                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
+                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
+                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
+                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
+                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
+                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
+                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
+                        IsMovValueFromStack(X86::VMOVDQU32Z256rm, X86::YMM0),
                         IsStackDeallocate(32)}));
 }
 
 TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) {
   const char ValueStr[] =
       "1111111122222222333333334444444455555555666666667777777788888888"
       "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000";
   EXPECT_THAT(
-      setRegTo(llvm::X86::ZMM0, APInt(512, ValueStr, 16)),
-      ElementsAreArray(
-          {IsStackAllocate(64),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 0),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xFFFFFFFFUL, 4),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xEEEEEEEEUL, 8),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xDDDDDDDDUL, 12),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xCCCCCCCCUL, 16),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xBBBBBBBBUL, 20),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0xAAAAAAAAUL, 24),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x99999999UL, 28),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 32),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 36),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 40),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 44),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 48),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 52),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 56),
-           IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 60),
-           IsMovValueFromStack(llvm::X86::VMOVDQU32Zrm, llvm::X86::ZMM0),
+      setRegTo(X86::ZMM0, APInt(512, ValueStr, 16)),
+      ElementsAreArray({IsStackAllocate(64),
+                        IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 0),
+                        IsMovValueToStack(X86::MOV32mi, 0xFFFFFFFFUL, 4),
+                        IsMovValueToStack(X86::MOV32mi, 0xEEEEEEEEUL, 8),
+                        IsMovValueToStack(X86::MOV32mi, 0xDDDDDDDDUL, 12),
+                        IsMovValueToStack(X86::MOV32mi, 0xCCCCCCCCUL, 16),
+                        IsMovValueToStack(X86::MOV32mi, 0xBBBBBBBBUL, 20),
+                        IsMovValueToStack(X86::MOV32mi, 0xAAAAAAAAUL, 24),
+                        IsMovValueToStack(X86::MOV32mi, 0x99999999UL, 28),
+                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 32),
+                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 36),
+                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 40),
+                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 44),
+                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 48),
+                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 52),
+                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 56),
+                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 60),
+                        IsMovValueFromStack(X86::VMOVDQU32Zrm, X86::ZMM0),
                         IsStackDeallocate(64)}));
 }
 
 // Note: We always put 80 bits on the stack independently of the size of the
 // value. This uses a bit more space but makes the code simpler.
 
 TEST_F(Core2TargetTest, SetRegToST0_32Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::ST0, APInt(32, 0x11112222ULL)),
+  EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
-                  OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
+                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToST1_32Bits) {
-  const MCInst CopySt0ToSt1 =
-      llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(llvm::X86::ST1);
-  EXPECT_THAT(
-      setRegTo(llvm::X86::ST1, APInt(32, 0x11112222ULL)),
+  const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);
+  EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
-                  OpcodeIs(llvm::X86::LD_F80m), CopySt0ToSt1,
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
+                          OpcodeIs(X86::LD_F80m), CopySt0ToSt1,
                           IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToST0_64Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::ST0, APInt(64, 0x1111222233334444ULL)),
+  EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
-                  OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
+                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToST0_80Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::ST0, APInt(80, "11112222333344445555", 16)),
+  EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8),
-                  OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
+                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToFP0_80Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::FP0, APInt(80, "11112222333344445555", 16)),
+  EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8),
-                  OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
+                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToFP1_32Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::FP1, APInt(32, 0x11112222ULL)),
+  EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
-                  OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
+                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2TargetTest, SetRegToFP1_4Bits) {
-  EXPECT_THAT(
-      setRegTo(llvm::X86::FP1, APInt(4, 0x1ULL)),
+  EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)),
               ElementsAre(IsStackAllocate(10),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x00000001UL, 0),
-                  IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
-                  IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
-                  OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10)));
+                          IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0),
+                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
+                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
+                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
   Instruction I(State.getInstrInfo(), State.getRATC(), X86::ADD64rm);
   InstructionTemplate IT(I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
   // Memory is operands 2-6.