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Differential D68538

GlobalISel: Partially implement lower for G_INSERT
ClosedPublic

Authored by arsenm on Oct 5 2019, 2:12 AM.

Details

Reviewers
aemerson
aditya_nandakumar
paquette
dsanders

Diff Detail

Event Timeline

arsenm created this revision.Oct 5 2019, 2:12 AM
Herald added subscribers: Petar.Avramovic, volkan, rovka and 3 others. · View Herald TranscriptOct 5 2019, 2:12 AM
arsenm added a parent revision: D68532: GlobalISel: Partially implement lower for G_EXTRACT.Oct 5 2019, 2:12 AM
dsanders accepted this revision.Oct 7 2019, 10:44 AM

LGTM

This revision is now accepted and ready to land.Oct 7 2019, 10:44 AM
arsenm closed this revision.Oct 7 2019, 12:11 PM

r373946

Revision Contents

PathSize
include/
llvm/
CodeGen/
GlobalISel/
1 line
lib/
CodeGen/
GlobalISel/
41 lines
Target/
AMDGPU/
10 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
154 lines

Diff 223367

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linespublic:
LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI); LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
LegalizeResult lowerFMad(MachineInstr &MI); LegalizeResult lowerFMad(MachineInstr &MI);
LegalizeResult lowerUnmergeValues(MachineInstr &MI); LegalizeResult lowerUnmergeValues(MachineInstr &MI);
LegalizeResult lowerShuffleVector(MachineInstr &MI); LegalizeResult lowerShuffleVector(MachineInstr &MI);
LegalizeResult lowerDynStackAlloc(MachineInstr &MI); LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
LegalizeResult lowerExtract(MachineInstr &MI); LegalizeResult lowerExtract(MachineInstr &MI);
LegalizeResult lowerInsert(MachineInstr &MI);
private: private:
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
const LegalizerInfo &LI; const LegalizerInfo &LI;
/// To keep track of changes made by the LegalizerHelper. /// To keep track of changes made by the LegalizerHelper.
GISelChangeObserver &Observer; GISelChangeObserver &Observer;
}; };
Show All 14 Lines

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 2,266 Lines • ▼ Show 20 Lines case TargetOpcode::G_SEXT_INREG: {
return Legalized; return Legalized;
} }
case G_SHUFFLE_VECTOR: case G_SHUFFLE_VECTOR:
return lowerShuffleVector(MI); return lowerShuffleVector(MI);
case G_DYN_STACKALLOC: case G_DYN_STACKALLOC:
return lowerDynStackAlloc(MI); return lowerDynStackAlloc(MI);
case G_EXTRACT: case G_EXTRACT:
return lowerExtract(MI); return lowerExtract(MI);
case G_INSERT:
return lowerInsert(MI);
} }
} }
LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
SmallVector<Register, 2> DstRegs; SmallVector<Register, 2> DstRegs;
unsigned NarrowSize = NarrowTy.getSizeInBits(); unsigned NarrowSize = NarrowTy.getSizeInBits();
▲ Show 20 Lines • Show All 1,930 Lines • ▼ Show 20 Lines if (DstTy.isScalar() &&
} }
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
return UnableToLegalize; return UnableToLegalize;
} }
LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
Register InsertSrc = MI.getOperand(2).getReg();
uint64_t Offset = MI.getOperand(3).getImm();
LLT DstTy = MRI.getType(Src);
LLT InsertTy = MRI.getType(InsertSrc);
if (InsertTy.isScalar() &&
(DstTy.isScalar() ||
(DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
LLT IntDstTy = DstTy;
if (!DstTy.isScalar()) {
IntDstTy = LLT::scalar(DstTy.getSizeInBits());
Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
}
Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
if (Offset != 0) {
auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
}
APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
InsertTy.getSizeInBits());
auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
MIRBuilder.buildBitcast(Dst, Or);
MI.eraseFromParent();
return Legalized;
}
return UnableToLegalize;
}

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 911 Lines • ▼ Show 20 Lines .unsupportedIf([=](const LegalityQuery &Query) {
return Query.Types[0] != EltTy; return Query.Types[0] != EltTy;
}); });
for (unsigned Op : {G_EXTRACT, G_INSERT}) { for (unsigned Op : {G_EXTRACT, G_INSERT}) {
unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0; unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0;
unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1; unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1;
// FIXME: Doesn't handle extract of illegal sizes. // FIXME: Doesn't handle extract of illegal sizes.
auto &Builder = getActionDefinitionsBuilder(Op); auto &Builder = getActionDefinitionsBuilder(Op)
.lowerIf(all(typeIs(LitTyIdx, S16), sizeIs(BigTyIdx, 32)))
// FIXME: Cleanup when G_INSERT lowering implemented. // FIXME: Multiples of 16 should not be legal.
if (Op == G_EXTRACT)
Builder.lowerIf(all(typeIs(LitTyIdx, S16), sizeIs(BigTyIdx, 32)));
Builder
.legalIf([=](const LegalityQuery &Query) { .legalIf([=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx]; const LLT BigTy = Query.Types[BigTyIdx];
const LLT LitTy = Query.Types[LitTyIdx]; const LLT LitTy = Query.Types[LitTyIdx];
return (BigTy.getSizeInBits() % 32 == 0) && return (BigTy.getSizeInBits() % 32 == 0) &&
(LitTy.getSizeInBits() % 16 == 0); (LitTy.getSizeInBits() % 16 == 0);
}) })
.widenScalarIf( .widenScalarIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
▲ Show 20 Lines • Show All 1,135 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir

Show First 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
name: test_insert_v2s16_s16_offset0 name: test_insert_v2s16_s16_offset0
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_v2s16_s16_offset0 ; CHECK-LABEL: name: test_insert_v2s16_s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s16>) = G_INSERT [[COPY]], [[TRUNC]](s16), 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: $vgpr0 = COPY [[INSERT]](<2 x s16>) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(<2 x s16>) = G_INSERT %0, %2, 0 %3:_(<2 x s16>) = G_INSERT %0, %2, 0
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
---
name: test_insert_v2s16_s16_offset1
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_v2s16_s16_offset1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65535
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(<2 x s16>) = G_INSERT %0, %2, 1
$vgpr0 = COPY %3
...
--- ---
name: test_insert_v2s16_s16_offset16 name: test_insert_v2s16_s16_offset16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_v2s16_s16_offset16 ; CHECK-LABEL: name: test_insert_v2s16_s16_offset16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s16>) = G_INSERT [[COPY]], [[TRUNC]](s16), 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: $vgpr0 = COPY [[INSERT]](<2 x s16>) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(<2 x s16>) = G_INSERT %0, %2, 16 %3:_(<2 x s16>) = G_INSERT %0, %2, 16
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: test_insert_v3s16_s16_offset0 name: test_insert_v3s16_s16_offset0
▲ Show 20 Lines • Show All 448 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 48 ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[TRUNC]](s16), 48
; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2 %1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(s64) = G_INSERT %0, %2, 48 %3:_(s64) = G_INSERT %0, %2, 48
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
---
name: test_insert_s32_s16_offset0
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_s32_s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(s32) = G_INSERT %1, %2, 0
$vgpr0 = COPY %3
...
---
name: test_insert_s32_s16_offset1
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_s32_s16_offset1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65535
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(s32) = G_INSERT %1, %2, 1
$vgpr0 = COPY %3
...
---
name: test_insert_s32_s16_offset8
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_s32_s16_offset8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65281
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(s32) = G_INSERT %1, %2, 8
$vgpr0 = COPY %3
...
---
name: test_insert_s32_s16_offset16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_insert_s32_s16_offset16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(s32) = G_INSERT %1, %2, 16
$vgpr0 = COPY %3
...