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[AArch64] Remove overlapping definitions (NFC)
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Authored by evandro on Oct 2 2019, 12:57 PM.

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pankajgode
joelkevinjones
ostannard

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rG42c8fae9d1b0: [AArch64] Remove overlapping scheduling definitions (NFC)

Summary

These definitions overlapped with others a few lines below. Somehow, they didn't raise errors before.

There seem to be other overlapping definitions. Somehow, they still don't raise errors.

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evandro created this revision.Oct 2 2019, 12:57 PM

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LGTM

This revision is now accepted and ready to land.Oct 18 2019, 2:28 AM

Closed by commit rG42c8fae9d1b0: [AArch64] Remove overlapping scheduling definitions (NFC) (authored by evandro). · Explain WhyOct 30 2019, 12:00 PM

This revision was automatically updated to reflect the committed changes.

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llvm/

lib/

Target/

AArch64/

AArch64SchedThunderX2T99.td

21 lines

Diff 222894

llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td

	Show First 20 Lines • Show All 1,511 Lines • ▼ Show 20 Lines
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>;			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>;

	// ASIMD move, integer immed			// ASIMD move, integer immed
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>;			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>;

	// ASIMD move, FP immed			// ASIMD move, FP immed
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>;			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>;

	// ASIMD table lookup, D-form
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8One")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Two")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Three")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Four")>;

	// ASIMD table lookup, Q-form
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8One")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Two")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Three")>;
	def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Four")>;

	// ASIMD transpose
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1", "^TRN2")>;

	// ASIMD unzip/zip
	def : InstRW<[THX2T99Write_5Cyc_F01],
	(instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;

	// ASIMD reciprocal estimate, D-form			// ASIMD reciprocal estimate, D-form
	// ASIMD reciprocal estimate, Q-form			// ASIMD reciprocal estimate, Q-form
	def : InstRW<[THX2T99Write_5Cyc_F01],			def : InstRW<[THX2T99Write_5Cyc_F01],
	(instregex "^FRECPEv", "^FRECPXv", "^URECPEv",			(instregex "^FRECPEv", "^FRECPXv", "^URECPEv",
	"^FRSQRTEv", "^URSQRTEv")>;			"^FRSQRTEv", "^URSQRTEv")>;

	// ASIMD reciprocal step, D-form, FZ			// ASIMD reciprocal step, D-form, FZ
	// ASIMD reciprocal step, D-form, no FZ			// ASIMD reciprocal step, D-form, no FZ
	Show All 19 Lines
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>;			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>;

	// ASIMD transpose			// ASIMD transpose
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1v", "^TRN2v",			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1v", "^TRN2v",
	"^UZP1v", "^UZP2v")>;			"^UZP1v", "^UZP2v")>;

	// ASIMD unzip/zip			// ASIMD unzip/zip
	def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>;			def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>;

	//--			//--
	// 3.15 ASIMD Load Instructions			// 3.15 ASIMD Load Instructions
	//--			//--

	// ASIMD load, 1 element, multiple, 1 reg, D-form			// ASIMD load, 1 element, multiple, 1 reg, D-form
	// ASIMD load, 1 element, multiple, 1 reg, Q-form			// ASIMD load, 1 element, multiple, 1 reg, Q-form
	def : InstRW<[THX2T99Write_4Cyc_LS01],			def : InstRW<[THX2T99Write_4Cyc_LS01],
	(instregex "^LD1Onev(8b\|4h\|2s\|1d\|16b\|8h\|4s\|2d)$")>;			(instregex "^LD1Onev(8b\|4h\|2s\|1d\|16b\|8h\|4s\|2d)$")>;
	▲ Show 20 Lines • Show All 297 Lines • Show Last 20 Lines