[AMDGPU][MC][GFX9][GFX10] Corrected parsing of optional operands

[dp]

Summary

See bug 43486: https://bugs.llvm.org/show_bug.cgi?id=43486

[dp]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

6089 ↗

(On Diff #222884)

This check is no longer necessary. Moreover it does not work for the following test because 'off' is not a register:

global_atomic_add v0, v[1:2], v2, off glc slc

[artem.tamazov]

Make it so!

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
   {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr},
   {"blgp", AMDGPUOperand::ImmTyBLGP, false, nullptr},
   {"cbsz", AMDGPUOperand::ImmTyCBSZ, false, nullptr},
   {"abid", AMDGPUOperand::ImmTyABID, false, nullptr}
 };
 
 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
-  unsigned size = Operands.size();
-  assert(size > 0);
 
   OperandMatchResultTy res = parseOptionalOpr(Operands);
 
   // This is a hack to enable hardcoded mandatory operands which follow
   // optional operands.
   //
   // Current design assumes that all operands after the first optional operand
   // are also optional. However implementation of some instructions violates
   // this rule (see e.g. flat/global atomic which have hardcoded 'glc' operands).
   //
   // To alleviate this problem, we have to (implicitly) parse extra operands
   // to make sure autogenerated parser of custom operands never hit hardcoded
   // mandatory operands.
 
-  if (size == 1 || ((AMDGPUOperand &)*Operands[size - 1]).isRegKind()) {
-
-    // We have parsed the first optional operand.
-    // Parse as many operands as necessary to skip all mandatory operands.
-
-    for (unsigned i = 0; i < MAX_OPR_LOOKAHEAD; ++i) {
-      if (res != MatchOperand_Success ||
-          getLexer().is(AsmToken::EndOfStatement)) break;
-      if (getLexer().is(AsmToken::Comma)) Parser.Lex();
-      res = parseOptionalOpr(Operands);
-    }
-  }
+        isToken(AsmToken::EndOfStatement))
+      break;
+
+    trySkipToken(AsmToken::Comma);
 
   return res;
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) {
   OperandMatchResultTy res;
   for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
     // try to parse any optional operand here

llvm/test/MC/AMDGPU/flat-global.s

 // GFX10: encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00]
 // GFX9: global_store_byte_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7f,0x00]
 // VI-ERR: instruction not supported on this GPU
 
 global_store_short_d16_hi v[3:4], v1, off
 // GFX10: encoding: [0x00,0x80,0x6c,0xdc,0x03,0x01,0x7d,0x00]
 // GFX9: global_store_short_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x6c,0xdc,0x03,0x01,0x7f,0x00]
 // VI-ERR: instruction not supported on this GPU
+
+global_atomic_add v0, v[1:2], v2, off glc slc
+// GFX10: global_atomic_add v0, v[1:2], v2, off glc slc ; encoding: [0x00,0x80,0xcb,0xdc,0x01,0x02,0x7d,0x00]
+// GFX9: global_atomic_add v0, v[1:2], v2, off glc slc ; encoding: [0x00,0x80,0x0b,0xdd,0x01,0x02,0x7f,0x00]
+// VI-ERR: error: invalid operand for instruction