AMDGPU: Propagate undef flag during pre-RA exec mask optimizations

[nhaehnle]

Summary

Issue: https://github.com/GPUOpen-Drivers/llpc/issues/204

[arsenm]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

262

I think there’s a getUndef

[nhaehnle]

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

262

I assume you mean getRegStateUndef.

[nhaehnle]

Use getRegStateUndef

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
 
   Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);
   Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
   MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
   if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
       Op1->getImm() != 0 || Op2->getImm() != 1)
     return AMDGPU::NoRegister;
 
-  LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t'
-                    << *Cmp << '\t' << *And);
+  LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
+                    << *And);
 
   Register CCReg = CC->getReg();
   LIS->RemoveMachineInstrFromMaps(*And);
-  MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
-                                TII->get(Andn2Opc), And->getOperand(0).getReg())
-                            .addReg(ExecReg)
-                            .addReg(CCReg, 0, CC->getSubReg());
+  MachineInstr *Andn2 =
+      BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
+              And->getOperand(0).getReg())
+          .addReg(CCReg, CC->isUndef() ? RegState::Undef : 0, CC->getSubReg());
   And->eraseFromParent();
   LIS->InsertMachineInstrInMaps(*Andn2);
 
   LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
 
   // Try to remove compare. Cmp value should not used in between of cmp
   // and s_and_b64 if VCC or just unused if any other register.
   if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) ||

llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
 
 # Check for regression from assuming an instruction was a copy after
 # dropping the opcode check.
 ---
 name: exec_src1_is_not_copy
 tracksRegLiveness: true
 machineFunctionInfo:
   isEntryFunction: true
body:             |
 
   bb.5:
     $exec = S_OR_B64 $exec, %9, implicit-def $scc
 
   bb.6:
     $exec = S_OR_B64 $exec, %7, implicit-def $scc
 
 ...
+
+# When folding a v_cndmask and a v_cmp in a pattern leading to
+# s_cbranch_vccz, ensure that an undef operand is handled correctly.
+---
+name: cndmask_cmp_cbranch_fold_undef
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x80000000)
+  ; GCN:   $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def $scc
+  ; GCN:   S_CBRANCH_VCCZ %bb.1, implicit $vcc
+  ; GCN: bb.1:
+  bb.0:
+
+    %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec
+    V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
+    $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
+    S_CBRANCH_VCCZ %bb.1, implicit $vcc
+
+  bb.1:
+
+...