[MC][ARM] vscclrm disassembles as vldmia

[labrinea]

Summary

Happens only when the mve.fp subtarget feature is enabled:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
	.text
	vldmia	pc, {d0, d1, d2, d3}
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
	.text
	vscclrm	{d0, d1, d2, d3, vpr}

Assembling returns the correct encoding with or without mve.fp:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
	.text
	vscclrm	{d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
	.text
	vscclrm	{d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]

The problem seems to be in the TableGen description of VSCCLRMD. The least significant bit should be set to zero.

[miyuki]

llvm/test/MC/ARM/vscclrm-asm.s

7 ↗

(On Diff #221755)

Why do we need a different prefix here? I.e. shouldn't the assembler behave the same way with "-mattr=+mve.fp,+8msecext" as with "-mattr=+8msecext"?
Same question the disassembler.

[labrinea]

llvm/test/MC/ARM/vscclrm-asm.s

7 ↗

(On Diff #221755)

Indeed, a separate label is not necessary. I will fix that.

[labrinea]

Updated the Filecheck labels as suggested.

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops),
                       AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,
                       "vscclrm{$p}\t$regs", "", []>, Sched<[]> {
   bits<13> regs;
   let Inst{31-23} = 0b111011001;
   let Inst{22} = regs{12};
   let Inst{21-16} = 0b011111;
   let Inst{15-12} = regs{11-8};
   let Inst{11-8} = 0b1011;
-  let Inst{7-0} = regs{7-0};
+  let Inst{7-1} = regs{7-1};
+  let Inst{0} = 0;
 
   let DecoderMethod = "DecodeVSCCLRM";
 
   list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt];
 }
 
 def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops),
                       AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,

llvm/trunk/test/MC/ARM/vscclrm-asm.s

 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding < %s 2>%t \
 // RUN: | FileCheck --check-prefix=CHECK %s
 // RUN:   FileCheck --check-prefix=ERROR < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK %s
+// RUN:   FileCheck --check-prefix=ERROR < %t %s
 // RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t
 // RUN: FileCheck --check-prefix=NOSEC < %t %s
 
 // CHECK: vscclrm            {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]
 // NOSEC: instruction requires: ARMv8-M Security Extensions
 vscclrm {s0-s3, vpr}
 
 // CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
 // NOSEC: instruction requires: ARMv8-M Security Extensions
 vscclrm {s3-s8, vpr}
 
 // CHECK: vscclrm            {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} @ encoding: [0x9f,0xec,0x0c,0x9a]
 vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
 
 // CHECK: vscclrm            {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]
 vscclrm {s31, vpr}
 
 // CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
 vscclrm {d0-d1, vpr}
 
+// CHECK: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]
+vscclrm {d0-d3, vpr}
+
 // CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
 vscclrm {d5-d7, vpr}
 
 // CHECK: it                 hi @ encoding: [0x88,0xbf]
 it hi
 // CHECK: vscclrmhi          {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} @ encoding: [0xdf,0xec,0x1d,0x1a]
 vscclrmhi {s3-s31, vpr}
 
 // ERROR: non-contiguous register range
 vscclrm {s0, s3-s4, vpr}
 
 // ERROR: register expected
 vscclrm {s32, vpr}
 
 // ERROR: invalid operand for instruction
 vscclrm {s0-s1}

llvm/trunk/test/MC/Disassembler/ARM/vscclrm.txt

 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding %s 2>&1 | FileCheck %s
-
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding %s 2>&1 | FileCheck %s
 
 [0x9f 0xec 0x04 0x0a]
 # CHECK: vscclrm {s0, s1, s2, s3, vpr}
 
 [0xdf,0xec,0x06,0x1a]
 # CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
 
 [0x9f 0xec 0x0c 0x9a]
 # CHECK: vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
 
 [0xdf 0xec 0x01 0xfa]
 # CHECK: vscclrm {s31, vpr}
 
 [0x9f,0xec,0x04,0x0b]
 # CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
 
+[0x9f,0xec,0x08,0x0b]
+# CHECK: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]
+
 [0x9f,0xec,0x06,0x5b]
 # CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
 
 [0x88 0xbf]
 # CHECK: it    hi
 
 [0xdf 0xec 0x1d 0x1a]
 # CHECK: vscclrmhi    {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}