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Differential D67798

[NFC][InstCombine] Add tests for shifty implementation of image clamping.
ClosedPublic

Authored by huihuiz on Sep 19 2019, 11:24 PM.

Details

Reviewers
lebedev.ri
efriedma
spatel
kparzysz
bcahoon
Commits
rG5b5f1c8efd67: [NFC][InstCombine] Add tests for shifty implementation of clamping.
rL372671: [NFC][InstCombine] Add tests for shifty implementation of clamping.
Summary

Clamp negative to zero and clamp positive to allOnesValue are common
operation in image saturation.
Add tests for shifty implementation of clamping, as prepare work for
folding:

and(ashr(subNSW(X, V), ScalarSizeInBits - 1), V) --> V s> 0 ? V : 0;

or(ashr(subNSW(X, V), ScalarSizeInBits - 1), V) --> V s> X ? AllOnesValue : V.

Diff Detail

Event Timeline

huihuiz created this revision.Sep 19 2019, 11:24 PM
huihuiz added a parent revision: D67799: [InstCombine] Fold a shifty implementation of clamp-to-zero..Sep 19 2019, 11:33 PM
huihuiz added a parent revision: D67800: [InstCombine] Fold a shifty implementation of clamp-to-allones.Sep 19 2019, 11:40 PM
huihuiz updated this revision to Diff 221144.Sep 20 2019, 6:02 PM

move test "extra_use_sub" to positive case

huihuiz updated this revision to Diff 221256.Sep 23 2019, 12:10 AM
huihuiz edited the summary of this revision. (Show Details)

make test more general

This revision was not accepted when it landed; it landed in state Needs Review.Sep 23 2019, 4:47 PM
Closed by commit rL372671: [NFC][InstCombine] Add tests for shifty implementation of clamping. (authored by huihuiz). · Explain Why
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
216 lines
249 lines

Diff 220951

llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine %s -S -o - | FileCheck %s
; clamp0 implemented in a shifty way, could be optimized as v < 0 ? 0 : v, where sub hasNoSignedWrap.
; int32 clamp0(int32 v) {
; return ((-(v) >> 31) & (v));
; }
;
; Scalar Types
define i8 @sub_ashr_and_i8(i8 %v) {
; CHECK-LABEL: @sub_ashr_and_i8(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7
; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHR]], [[V]]
; CHECK-NEXT: ret i8 [[AND]]
;
%sub = sub nsw i8 0, %v
%shr = ashr i8 %sub, 7
%and = and i8 %shr, %v
ret i8 %and
}
define i16 @sub_ashr_and_i16(i16 %v) {
; CHECK-LABEL: @sub_ashr_and_i16(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15
; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHR]], [[V]]
; CHECK-NEXT: ret i16 [[AND]]
;
%sub = sub nsw i16 0, %v
%shr = ashr i16 %sub, 15
%and = and i16 %shr, %v
ret i16 %and
}
define i32 @sub_ashr_and_i32(i32 %v) {
; CHECK-LABEL: @sub_ashr_and_i32(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
%shr = ashr i32 %sub, 31
%and = and i32 %shr, %v
ret i32 %and
}
define i64 @sub_ashr_and_i64(i64 %v) {
; CHECK-LABEL: @sub_ashr_and_i64(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63
; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHR]], [[V]]
; CHECK-NEXT: ret i64 [[AND]]
;
%sub = sub nsw i64 0, %v
%shr = ashr i64 %sub, 63
%and = and i64 %shr, %v
ret i64 %and
}
; nuw nsw
define i32 @sub_ashr_and_i32_nuw_nsw(i32 %v) {
; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw(
; CHECK-NEXT: ret i32 0
;
%sub = sub nuw nsw i32 0, %v
%shr = ashr i32 %sub, 31
%and = and i32 %shr, %v
ret i32 %and
}
; Commute
define i32 @sub_ashr_and_i32_commute(i32 %v) {
; CHECK-LABEL: @sub_ashr_and_i32_commute(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
%shr = ashr i32 %sub, 31
%and = and i32 %v, %shr ; commute %v and %shr
ret i32 %and
}
; Vector Types
define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_and_i32_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nsw <4 x i32> zeroinitializer, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%and = and <4 x i32> %shr, %v
ret <4 x i32> %and
}
define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw(
; CHECK-NEXT: ret <4 x i32> zeroinitializer
;
%sub = sub nuw nsw <4 x i32> zeroinitializer, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%and = and <4 x i32> %shr, %v
ret <4 x i32> %and
}
define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nsw <4 x i32> zeroinitializer, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%and = and <4 x i32> %v, %shr ; commute %v and %shr
ret <4 x i32> %and
}
; Extra uses
define i32 @sub_ashr_and_i32_extra_use_and(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
%shr = ashr i32 %sub, 31
%and = and i32 %shr, %v
store i32 %and, i32* %p
ret i32 %and
}
; Negative Tests
define i32 @sub_ashr_and_i32_extra_use_sub(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
store i32 %sub, i32* %p
%shr = ashr i32 %sub, 31
%and = and i32 %shr, %v
ret i32 %and
}
define i32 @sub_ashr_and_i32_extra_use_ashr(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_and_i32_extra_use_ashr(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
%shr = ashr i32 %sub, 31
store i32 %shr, i32* %p
%and = and i32 %shr, %v
ret i32 %and
}
define i32 @sub_ashr_and_i32_no_nuw_nsw(i32 %v) {
; CHECK-LABEL: @sub_ashr_and_i32_no_nuw_nsw(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 7
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub i32 0, %v
%shr = ashr i32 %sub, 7
%and = and i32 %shr, %v
ret i32 %and
}
define <4 x i32> @sub_ashr_and_i32_vec_undef(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_and_i32_vec_undef(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 undef>
; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nsw <4 x i32> zeroinitializer, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 undef>
%and = and <4 x i32> %shr, %v
ret <4 x i32> %and
}
define i32 @sub_ashr_and_i32_shift_wrong_bit(i32 %v) {
; CHECK-LABEL: @sub_ashr_and_i32_shift_wrong_bit(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 15
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 0, %v
%shr = ashr i32 %sub, 15
%and = and i32 %shr, %v
ret i32 %and
}

llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine %s -S -o - | FileCheck %s
; clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap.
; int32 clamp255(int32 v) {
; return (((255 - (v)) >> 31) | (v)) & 255;
; }
;
; Scalar Types
define i32 @clamp255_i32(i32 %v) {
; CHECK-LABEL: @clamp255_i32(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR]], 255
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
%and = and i32 %or, 255
ret i32 %and
}
define i8 @sub_ashr_or_i8(i8 %v) {
; CHECK-LABEL: @sub_ashr_or_i8(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 15, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7
; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHR]], [[V]]
; CHECK-NEXT: ret i8 [[OR]]
;
%sub = sub nsw i8 15, %v
%shr = ashr i8 %sub, 7
%or = or i8 %shr, %v
ret i8 %or
}
define i16 @sub_ashr_or_i16(i16 %v) {
; CHECK-LABEL: @sub_ashr_or_i16(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15
; CHECK-NEXT: [[OR:%.*]] = or i16 [[SHR]], [[V]]
; CHECK-NEXT: ret i16 [[OR]]
;
%sub = sub nsw i16 255, %v
%shr = ashr i16 %sub, 15
%or = or i16 %shr, %v
ret i16 %or
}
define i32 @sub_ashr_or_i32(i32 %v) {
; CHECK-LABEL: @sub_ashr_or_i32(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
ret i32 %or
}
define i64 @sub_ashr_or_i64(i64 %v) {
; CHECK-LABEL: @sub_ashr_or_i64(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 65535, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63
; CHECK-NEXT: [[OR:%.*]] = or i64 [[SHR]], [[V]]
; CHECK-NEXT: ret i64 [[OR]]
;
%sub = sub nsw i64 65535, %v
%shr = ashr i64 %sub, 63
%or = or i64 %shr, %v
ret i64 %or
}
; nuw nsw
define i32 @sub_ashr_or_i32_nuw_nsw(i32 %v) {
; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw(
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nuw nsw i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
ret i32 %or
}
; Commute
define i32 @sub_ashr_or_i32_commute(i32 %v) {
; CHECK-LABEL: @sub_ashr_or_i32_commute(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %v, %shr ; commute %shr and %v
ret i32 %or
}
; Vector Types
define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_or_i32_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%or = or <4 x i32> %shr, %v
ret <4 x i32> %or
}
define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw(
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%sub = sub nuw nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%or = or <4 x i32> %shr, %v
ret <4 x i32> %or
}
define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_or_i32_vec_commute(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%or = or <4 x i32> %v, %shr
ret <4 x i32> %or
}
; Extra uses
define i32 @sub_ashr_or_i32_extra_use_or(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: store i32 [[OR]], i32* [[P:%.*]], align 4
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
store i32 %or, i32* %p
ret i32 %or
}
; Negative Tests
define i32 @sub_ashr_or_i32_extra_use_sub(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_sub(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
store i32 %sub, i32* %p
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
ret i32 %or
}
define i32 @sub_ashr_or_i32_extra_use_ashr(i32 %v, i32* %p) {
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_ashr(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 31
store i32 %shr, i32* %p
%or = or i32 %shr, %v
ret i32 %or
}
define i32 @sub_ashr_or_i32_no_nsw_nuw(i32 %v) {
; CHECK-LABEL: @sub_ashr_or_i32_no_nsw_nuw(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub i32 255, %v
%shr = ashr i32 %sub, 31
%or = or i32 %shr, %v
ret i32 %or
}
define <4 x i32> @sub_ashr_or_i32_vec_undef1(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_or_i32_vec_undef1(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%sub = sub nsw <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, %v
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
%or = or <4 x i32> %shr, %v
ret <4 x i32> %or
}
define <4 x i32> @sub_ashr_or_i32_vec_undef2(<4 x i32> %v) {
; CHECK-LABEL: @sub_ashr_or_i32_vec_undef2(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 undef, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
%shr = ashr <4 x i32> %sub, <i32 undef, i32 31, i32 31, i32 31>
%or = or <4 x i32> %shr, %v
ret <4 x i32> %or
}
define i32 @sub_ashr_or_i32_shift_wrong_bit(i32 %v) {
; CHECK-LABEL: @sub_ashr_or_i32_shift_wrong_bit(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 11
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sub = sub nsw i32 255, %v
%shr = ashr i32 %sub, 11
%or = or i32 %shr, %v
ret i32 %or
}