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committedSep 23, 2019
[NFC][InstCombine] Add tests for shifty implementation of clamping.
Summary: Clamp negative to zero and clamp positive to allOnes are common operation in image saturation. Add tests for shifty implementation of clamping, as prepare work for folding: and(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) --> X s> 0 ? X : 0; or(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) --> X s> Y ? allOnes : X. Reviewers: lebedev.ri, efriedma, spatel, kparzysz, bcahoon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67798 llvm-svn: 372671
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine %s -S -o - | FileCheck %s
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; Clamp negative to zero:
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; E.g., clamp0 implemented in a shifty way, could be optimized as v > 0 ? v : 0, where sub hasNoSignedWrap.
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; int32 clamp0(int32 v) {
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; return ((-(v) >> 31) & (v));
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; }
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;
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; Scalar Types
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define i8 @sub_ashr_and_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: @sub_ashr_and_i8(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7
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; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHR]], [[X]]
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; CHECK-NEXT: ret i8 [[AND]]
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;
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%sub = sub nsw i8 %y, %x
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%shr = ashr i8 %sub, 7
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%and = and i8 %shr, %x
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ret i8 %and
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}
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define i16 @sub_ashr_and_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: @sub_ashr_and_i16(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15
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; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHR]], [[X]]
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; CHECK-NEXT: ret i16 [[AND]]
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;
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%sub = sub nsw i16 %y, %x
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%shr = ashr i16 %sub, 15
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%and = and i16 %shr, %x
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ret i16 %and
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}
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define i32 @sub_ashr_and_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i64 @sub_ashr_and_i64(i64 %x, i64 %y) {
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; CHECK-LABEL: @sub_ashr_and_i64(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHR]], [[X]]
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; CHECK-NEXT: ret i64 [[AND]]
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;
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%sub = sub nsw i64 %y, %x
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%shr = ashr i64 %sub, 63
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%and = and i64 %shr, %x
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ret i64 %and
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}
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; nuw nsw
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define i32 @sub_ashr_and_i32_nuw_nsw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nuw nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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; Commute
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define i32 @sub_ashr_and_i32_commute(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_commute(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %x, %shr ; commute %x and %shr
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ret i32 %and
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}
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; Vector Types
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define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nuw nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %x, %shr ; commute %x and %shr
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ret <4 x i32> %and
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}
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; Extra uses
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define i32 @sub_ashr_and_i32_extra_use_sub(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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store i32 %sub, i32* %p
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i32 @sub_ashr_and_i32_extra_use_and(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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store i32 %and, i32* %p
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ret i32 %and
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}
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; Negative Tests
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define i32 @sub_ashr_and_i32_extra_use_ashr(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_ashr(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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store i32 %shr, i32* %p
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i32 @sub_ashr_and_i32_no_nuw_nsw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_no_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 7
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub i32 %y, %x
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%shr = ashr i32 %sub, 7
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_undef(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_undef(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 undef>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 undef>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define i32 @sub_ashr_and_i32_shift_wrong_bit(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_shift_wrong_bit(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 15
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 15
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%and = and i32 %shr, %x
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ret i32 %and
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}
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine %s -S -o - | FileCheck %s
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; Clamp positive to allOnes:
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; E.g., clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap.
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; int32 clamp255(int32 v) {
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; return (((255 - (v)) >> 31) | (v)) & 255;
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; }
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;
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; Scalar Types
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define i32 @clamp255_i32(i32 %x) {
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; CHECK-LABEL: @clamp255_i32(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 255, [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR]], 255
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 255, %x
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%shr = ashr i32 %sub, 31
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%or = or i32 %shr, %x
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%and = and i32 %or, 255
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ret i32 %and
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}
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define i8 @sub_ashr_or_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: @sub_ashr_or_i8(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7
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; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHR]], [[X]]
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; CHECK-NEXT: ret i8 [[OR]]
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;
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%sub = sub nsw i8 %y, %x
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%shr = ashr i8 %sub, 7
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%or = or i8 %shr, %x
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ret i8 %or
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}
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define i16 @sub_ashr_or_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: @sub_ashr_or_i16(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15
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; CHECK-NEXT: [[OR:%.*]] = or i16 [[SHR]], [[X]]
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; CHECK-NEXT: ret i16 [[OR]]
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;
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%sub = sub nsw i16 %y, %x
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%shr = ashr i16 %sub, 15
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%or = or i16 %shr, %x
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ret i16 %or
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}
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define i32 @sub_ashr_or_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_or_i32(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%or = or i32 %shr, %x
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ret i32 %or
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}
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define i64 @sub_ashr_or_i64(i64 %x, i64 %y) {
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; CHECK-LABEL: @sub_ashr_or_i64(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63
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; CHECK-NEXT: [[OR:%.*]] = or i64 [[SHR]], [[X]]
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; CHECK-NEXT: ret i64 [[OR]]
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;
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%sub = sub nsw i64 %y, %x
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%shr = ashr i64 %sub, 63
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%or = or i64 %shr, %x
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ret i64 %or
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}
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; nuw nsw
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define i32 @sub_ashr_or_i32_nuw_nsw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nuw nsw i32 %y, %x
90+
%shr = ashr i32 %sub, 31
91+
%or = or i32 %shr, %x
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ret i32 %or
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}
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; Commute
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define i32 @sub_ashr_or_i32_commute(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_commute(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
106+
%or = or i32 %x, %shr ; commute %shr and %x
107+
ret i32 %or
108+
}
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; Vector Types
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define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_vec(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]
117+
; CHECK-NEXT: ret <4 x i32> [[OR]]
118+
;
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%sub = sub nsw <4 x i32> %y, %x
120+
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
121+
%or = or <4 x i32> %shr, %x
122+
ret <4 x i32> %or
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}
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define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[OR]]
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;
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%sub = sub nuw nsw <4 x i32> %y, %x
133+
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
134+
%or = or <4 x i32> %shr, %x
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ret <4 x i32> %or
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}
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define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
139+
; CHECK-LABEL: @sub_ashr_or_i32_vec_commute(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[OR]]
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;
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%sub = sub nsw <4 x i32> %y, %x
146+
%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
147+
%or = or <4 x i32> %x, %shr
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ret <4 x i32> %or
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}
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; Extra uses
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define i32 @sub_ashr_or_i32_extra_use_sub(i32 %x, i32 %y, i32* %p) {
154+
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_sub(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
162+
store i32 %sub, i32* %p
163+
%shr = ashr i32 %sub, 31
164+
%or = or i32 %shr, %x
165+
ret i32 %or
166+
}
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168+
define i32 @sub_ashr_or_i32_extra_use_or(i32 %x, i32 %y, i32* %p) {
169+
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
173+
; CHECK-NEXT: store i32 [[OR]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
178+
%or = or i32 %shr, %x
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store i32 %or, i32* %p
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ret i32 %or
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}
182+
183+
; Negative Tests
184+
185+
define i32 @sub_ashr_or_i32_extra_use_ashr(i32 %x, i32 %y, i32* %p) {
186+
; CHECK-LABEL: @sub_ashr_or_i32_extra_use_ashr(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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store i32 %shr, i32* %p
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%or = or i32 %shr, %x
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ret i32 %or
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}
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define i32 @sub_ashr_or_i32_no_nsw_nuw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_no_nsw_nuw(
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub i32 %y, %x
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%shr = ashr i32 %sub, 31
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%or = or i32 %shr, %x
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ret i32 %or
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}
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define <4 x i32> @sub_ashr_or_i32_vec_undef1(<4 x i32> %x) {
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; CHECK-LABEL: @sub_ashr_or_i32_vec_undef1(
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; CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[OR]]
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;
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%sub = sub <4 x i32> <i32 255, i32 255, i32 undef, i32 255>, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%or = or <4 x i32> %shr, %x
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ret <4 x i32> %or
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}
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define <4 x i32> @sub_ashr_or_i32_vec_undef2(<4 x i32> %x) {
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; CHECK-LABEL: @sub_ashr_or_i32_vec_undef2(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 undef, i32 31, i32 31, i32 31>
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; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[OR]]
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;
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%sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %x
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%shr = ashr <4 x i32> %sub, <i32 undef, i32 31, i32 31, i32 31>
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%or = or <4 x i32> %shr, %x
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ret <4 x i32> %or
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}
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define i32 @sub_ashr_or_i32_shift_wrong_bit(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_or_i32_shift_wrong_bit(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 11
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[OR]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 11
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%or = or i32 %shr, %x
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ret i32 %or
250+
}

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