[WebAssembly] vNxM.load_splat instructions

[tlively]

Summary

Adds the new load_splat instructions as specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#load-and-splat.

DAGISel does not allow matching multiple copies of the same load in a
single pattern, so we use a new node in WebAssemblyISD to wrap loads
that should be splatted.

Depends on D67783.

[tlively]

• Add encoding tests

[aheejin]

Mostly LGTM. By the way this contains diff of D67783 as well.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

62 ↗

(On Diff #221072)

I asked the same question in D67783, but why do we not need SIMD128? Other parts below too

75 ↗

(On Diff #221072)

Don't we need SDTCisPtrTy<0>?

78 ↗

(On Diff #221072)

Do we only do zero extension for splats?

83 ↗

(On Diff #221072)

Didn't know we can use foreach like this :D

[tlively]

• Rebase

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

62 ↗

(On Diff #221072)

HasUnimplementedSIMD128 implies HasSIMD128, so having both is redundant.

75 ↗

(On Diff #221072)

No, the argument to wasm_load_splat is actually the result of the original load, so it is not necessarily an i32. It could also be an i64, f32, or f64. The type checking of the pointer is handled by the extloadi8, extloadi16, and load nodes.

78 ↗

(On Diff #221072)

We do undefined extension for splats, since the high bits are never observed. Only the original bits end up in the splatted vector.

llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
+  case WebAssembly::LOAD_SPLAT_v8x16:
+  case WebAssembly::LOAD_SPLAT_v8x16_S:
     return 0;
   case WebAssembly::LOAD16_S_I32:
   case WebAssembly::LOAD16_S_I32_S:
   case WebAssembly::LOAD16_U_I32:
   case WebAssembly::LOAD16_U_I32_S:
   case WebAssembly::LOAD16_S_I64:
   case WebAssembly::LOAD16_S_I64_S:
   case WebAssembly::LOAD16_U_I64:
inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
+  case WebAssembly::LOAD_SPLAT_v16x8:
+  case WebAssembly::LOAD_SPLAT_v16x8_S:
     return 1;
   case WebAssembly::LOAD_I32:
   case WebAssembly::LOAD_I32_S:
   case WebAssembly::LOAD_F32:
   case WebAssembly::LOAD_F32_S:
   case WebAssembly::STORE_I32:
   case WebAssembly::STORE_I32_S:
   case WebAssembly::STORE_F32:
inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
   case WebAssembly::ATOMIC_NOTIFY:
   case WebAssembly::ATOMIC_NOTIFY_S:
   case WebAssembly::ATOMIC_WAIT_I32:
   case WebAssembly::ATOMIC_WAIT_I32_S:
+  case WebAssembly::LOAD_SPLAT_v32x4:
+  case WebAssembly::LOAD_SPLAT_v32x4_S:
     return 2;
   case WebAssembly::LOAD_I64:
   case WebAssembly::LOAD_I64_S:
   case WebAssembly::LOAD_F64:
   case WebAssembly::LOAD_F64_S:
   case WebAssembly::STORE_I64:
   case WebAssembly::STORE_I64_S:
   case WebAssembly::STORE_F64:
inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   case WebAssembly::ATOMIC_RMW_XOR_I64:
   case WebAssembly::ATOMIC_RMW_XOR_I64_S:
   case WebAssembly::ATOMIC_RMW_XCHG_I64:
   case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
   case WebAssembly::ATOMIC_WAIT_I64:
   case WebAssembly::ATOMIC_WAIT_I64_S:
+  case WebAssembly::LOAD_SPLAT_v64x2:
+  case WebAssembly::LOAD_SPLAT_v64x2_S:
     return 3;
   case WebAssembly::LOAD_v16i8:
   case WebAssembly::LOAD_v16i8_S:
   case WebAssembly::LOAD_v8i16:
   case WebAssembly::LOAD_v8i16_S:
   case WebAssembly::LOAD_v4i32:
   case WebAssembly::LOAD_v4i32_S:
   case WebAssembly::LOAD_v2i64:

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def

 // access.
 HANDLE_NODETYPE(WrapperPIC)
 HANDLE_NODETYPE(BR_IF)
 HANDLE_NODETYPE(BR_TABLE)
 HANDLE_NODETYPE(SHUFFLE)
 HANDLE_NODETYPE(VEC_SHL)
 HANDLE_NODETYPE(VEC_SHR_S)
 HANDLE_NODETYPE(VEC_SHR_U)
+HANDLE_NODETYPE(LOAD_SPLAT)
 HANDLE_NODETYPE(THROW)
 HANDLE_NODETYPE(MEMORY_COPY)
 HANDLE_NODETYPE(MEMORY_FILL)
 
 // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

if (ConstInitBytes < SplatInitBytes) {
         if (!Lane.isUndef() && !IsConstant(Lane))
           Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
                                DAG.getConstant(I, DL, MVT::i32));
       }
       return Result;
     }
   }
   // Use a splat for the initial vector
-  SDValue Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
+  SDValue Result;
+  // Possibly a load_splat
+  LoadSDNode *SplattedLoad;
+  if (Subtarget->hasUnimplementedSIMD128() &&
+      (SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
+      SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) {
+    Result = DAG.getNode(WebAssemblyISD::LOAD_SPLAT, DL, VecT, SplatValue);
+  } else {
+    Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
+  }
   // Add replace_lane instructions for other values
   for (size_t I = 0; I < Lanes; ++I) {
     const SDValue &Lane = Op->getOperand(I);
     if (Lane != SplatValue)
       Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
                            DAG.getConstant(I, DL, MVT::i32));
   }
   return Result;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
 def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 }
 
+// vNxM.load_splat
+multiclass SIMDLoadSplat<string vec, bits<32> simdop> {
+  let mayLoad = 1, UseNamedOperandTable = 1,
+      Predicates = [HasUnimplementedSIMD128] in
+  defm LOAD_SPLAT_#vec :
+    SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
+           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
+           vec#".load_splat\t$dst, ${off}(${addr})$p2align",
+           vec#".load_splat\t$off$p2align", simdop>;
+}
+
+defm "" : SIMDLoadSplat<"v8x16", 194>;
+defm "" : SIMDLoadSplat<"v16x8", 195>;
+defm "" : SIMDLoadSplat<"v32x4", 196>;
+defm "" : SIMDLoadSplat<"v64x2", 197>;
+
+def wasm_load_splat_t : SDTypeProfile<1, 1, []>;
+def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t>;
+
+foreach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32", "extloadi16"],
+                ["v4i32", "i32", "load"], ["v2i64", "i64", "load"],
+                ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in
+def load_splat_#args[0] :
+  PatFrag<(ops node:$addr), (wasm_load_splat
+            (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2]) node:$addr)))>;
+
+let Predicates = [HasUnimplementedSIMD128] in
+foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
+                ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
+def : LoadPatNoOffset<!cast<ValueType>(args[0]),
+                      !cast<PatFrag>("load_splat_"#args[0]),
+                      !cast<NI>("LOAD_SPLAT_"#args[1])>;
+def : LoadPatImmOff<!cast<ValueType>(args[0]),
+                    !cast<PatFrag>("load_splat_"#args[0]),
+                    regPlusImm,
+                    !cast<NI>("LOAD_SPLAT_"#args[1])>;
+def : LoadPatImmOff<!cast<ValueType>(args[0]),
+                    !cast<PatFrag>("load_splat_"#args[0]),
+                    or_is_add,
+                    !cast<NI>("LOAD_SPLAT_"#args[1])>;
+def : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
+                        !cast<PatFrag>("load_splat_"#args[0]),
+                        !cast<NI>("LOAD_SPLAT_"#args[1])>;
+def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
+                               !cast<PatFrag>("load_splat_"#args[0]),
+                               !cast<NI>("LOAD_SPLAT_"#args[1])>;
+}
+
 // Store: v128.store
 multiclass SIMDStore<ValueType vec_t> {
   let mayStore = 1, UseNamedOperandTable = 1 in
   defm STORE_#vec_t :
     SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
            "v128.store\t${off}(${addr})$p2align, $vec",
            "v128.store\t$off$p2align", 1>;

llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll

 ; SIMD128-NEXT: .functype load_v16i8 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8(<16 x i8>* %p) {
   %v = load <16 x i8>, <16 x i8>* %p
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8:
+; SIMD128-VM-NOT: v8x16.load_splat
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8(i8* %p) {
+  %e = load i8, i8* %p
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_folded_offset(<16 x i8>* %p) {
   %q = ptrtoint <16 x i8>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_with_folded_offset(i8* %p) {
+  %q = ptrtoint i8* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to i8*
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_folded_gep_offset(<16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 1($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_with_folded_gep_offset(i8* %p) {
+  %s = getelementptr inbounds i8, i8* %p, i32 1
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_gep_negative_offset(<16 x i8>* %p) {
   %s = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i32 -1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_with_unfolded_gep_negative_offset(i8* %p) {
+  %s = getelementptr inbounds i8, i8* %p, i32 -1
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_offset(<16 x i8>* %p) {
   %q = ptrtoint <16 x i8>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_with_unfolded_offset(i8* %p) {
+  %q = ptrtoint i8* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to i8*
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_with_unfolded_gep_offset(<16 x i8>* %p) {
   %s = getelementptr <16 x i8>, <16 x i8>* %p, i32 1
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 1{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_with_unfolded_gep_offset(i8* %p) {
+  %s = getelementptr i8, i8* %p, i32 1
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_v16i8_from_numeric_address() {
   %s = inttoptr i32 32 to <16 x i8>*
   %v = load <16 x i8>, <16 x i8>* %s
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @load_splat_v16i8_from_numeric_address() {
+  %s = inttoptr i32 32 to i8*
+  %e = load i8, i8* %s
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: load_v16i8_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v16i8_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v16i8($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v16i8 = global <16 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
 define <16 x i8> @load_v16i8_from_global_address() {
   %v = load <16 x i8>, <16 x i8>* @gv_v16i8
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: load_splat_v16i8_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v16i8_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, gv_i8($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_i8 = global i8 42
+define <16 x i8> @load_splat_v16i8_from_global_address() {
+  %e = load i8, i8* @gv_i8
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  ret <16 x i8> %v2
+}
+
 ; CHECK-LABEL: store_v16i8:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype store_v16i8 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v16i8(<16 x i8> %v, <16 x i8>* %p) {
   store <16 x i8> %v , <16 x i8>* %p
   ret void
 }

 ; SIMD128-NEXT: .functype load_v8i16 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16(<8 x i16>* %p) {
   %v = load <8 x i16>, <8 x i16>* %p
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16(i16* %p) {
+  %e = load i16, i16* %p
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_folded_offset(<8 x i16>* %p) {
   %q = ptrtoint <8 x i16>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16_with_folded_offset(i16* %p) {
+  %q = ptrtoint i16* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to i16*
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_folded_gep_offset(<8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 2($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16_with_folded_gep_offset(i16* %p) {
+  %s = getelementptr inbounds i16, i16* %p, i32 1
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_gep_negative_offset(<8 x i16>* %p) {
   %s = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i32 -1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -2{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16_with_unfolded_gep_negative_offset(i16* %p) {
+  %s = getelementptr inbounds i16, i16* %p, i32 -1
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[L0]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_offset(<8 x i16>* %p) {
   %q = ptrtoint <8 x i16>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[L0]]{{$}}
+define <8 x i16> @load_splat_v8i16_with_unfolded_offset(i16* %p) {
+  %q = ptrtoint i16* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to i16*
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_with_unfolded_gep_offset(<8 x i16>* %p) {
   %s = getelementptr <8 x i16>, <8 x i16>* %p, i32 1
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 2{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16_with_unfolded_gep_offset(i16* %p) {
+  %s = getelementptr i16, i16* %p, i32 1
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_v8i16_from_numeric_address() {
   %s = inttoptr i32 32 to <8 x i16>*
   %v = load <8 x i16>, <8 x i16>* %s
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_splat_v8i16_from_numeric_address() {
+  %s = inttoptr i32 32 to i16*
+  %e = load i16, i16* %s
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: load_v8i16_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v8i16_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v8i16($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v8i16 = global <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
 define <8 x i16> @load_v8i16_from_global_address() {
   %v = load <8 x i16>, <8 x i16>* @gv_v8i16
   ret <8 x i16> %v
 }
 
+; CHECK-LABEL: load_splat_v8i16_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v8i16_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, gv_i16($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_i16 = global i16 42
+define <8 x i16> @load_splat_v8i16_from_global_address() {
+  %e = load i16, i16* @gv_i16
+  %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
+  %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> zeroinitializer
+  ret <8 x i16> %v2
+}
+
 ; CHECK-LABEL: store_v8i16:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype store_v8i16 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v8i16(<8 x i16> %v, <8 x i16>* %p) {
   store <8 x i16> %v , <8 x i16>* %p
   ret void
 }

 ; SIMD128-NEXT: .functype load_v4i32 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32(<4 x i32>* %p) {
   %v = load <4 x i32>, <4 x i32>* %p
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat
+define <4 x i32> @load_splat_v4i32(i32* %addr) {
+  %e = load i32, i32* %addr, align 4
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_folded_offset(<4 x i32>* %p) {
   %q = ptrtoint <4 x i32>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_with_folded_offset(i32* %p) {
+  %q = ptrtoint i32* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to i32*
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_folded_gep_offset(<4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 4($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_with_folded_gep_offset(i32* %p) {
+  %s = getelementptr inbounds i32, i32* %p, i32 1
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_gep_negative_offset(<4 x i32>* %p) {
   %s = getelementptr inbounds <4 x i32>, <4 x i32>* %p, i32 -1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -4{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_with_unfolded_gep_negative_offset(i32* %p) {
+  %s = getelementptr inbounds i32, i32* %p, i32 -1
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_offset(<4 x i32>* %p) {
   %q = ptrtoint <4 x i32>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_with_unfolded_offset(i32* %p) {
+  %q = ptrtoint i32* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to i32*
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_with_unfolded_gep_offset(<4 x i32>* %p) {
   %s = getelementptr <4 x i32>, <4 x i32>* %p, i32 1
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 4{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_with_unfolded_gep_offset(i32* %p) {
+  %s = getelementptr i32, i32* %p, i32 1
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_v4i32_from_numeric_address() {
   %s = inttoptr i32 32 to <4 x i32>*
   %v = load <4 x i32>, <4 x i32>* %s
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_splat_v4i32_from_numeric_address() {
+  %s = inttoptr i32 32 to i32*
+  %e = load i32, i32* %s
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: load_v4i32_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4i32_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v4i32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v4i32 = global <4 x i32> <i32 42, i32 42, i32 42, i32 42>
 define <4 x i32> @load_v4i32_from_global_address() {
   %v = load <4 x i32>, <4 x i32>* @gv_v4i32
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: load_splat_v4i32_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4i32_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, gv_i32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_i32 = global i32 42
+define <4 x i32> @load_splat_v4i32_from_global_address() {
+  %e = load i32, i32* @gv_i32
+  %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
+  %v2 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %v2
+}
+
 ; CHECK-LABEL: store_v4i32:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype store_v4i32 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v4i32(<4 x i32> %v, <4 x i32>* %p) {
   store <4 x i32> %v , <4 x i32>* %p
   ret void
 }

 ; SIMD128-NEXT: .functype load_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64(<2 x i64>* %p) {
   %v = load <2 x i64>, <2 x i64>* %p
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64(i64* %p) {
+  %e = load i64, i64* %p
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_with_folded_offset(i64* %p) {
+  %q = ptrtoint i64* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to i64*
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_with_folded_gep_offset(i64* %p) {
+  %s = getelementptr inbounds i64, i64* %p, i32 1
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_negative_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_with_unfolded_gep_negative_offset(i64* %p) {
+  %s = getelementptr inbounds i64, i64* %p, i32 -1
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_with_unfolded_offset(i64* %p) {
+  %q = ptrtoint i64* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to i64*
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_with_unfolded_gep_offset(i64* %p) {
+  %s = getelementptr i64, i64* %p, i32 1
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_splat_v2i64_from_numeric_address() {
+  %s = inttoptr i32 32 to i64*
+  %e = load i64, i64* %s
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: load_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2i64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2i64 = global <2 x i64> <i64 42, i64 42>
 define <2 x i64> @load_v2i64_from_global_address() {
   %v = load <2 x i64>, <2 x i64>* @gv_v2i64
   ret <2 x i64> %v
 }
 
+; CHECK-LABEL: load_splat_v2i64_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2i64_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_i64($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_i64 = global i64 42
+define <2 x i64> @load_splat_v2i64_from_global_address() {
+  %e = load i64, i64* @gv_i64
+  %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
+  %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %v2
+}
+
 ; CHECK-LABEL: store_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2i64(<2 x i64> %v, <2 x i64>* %p) {
   store <2 x i64> %v , <2 x i64>* %p
   ret void

 ; SIMD128-NEXT: .functype load_v4f32 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32(<4 x float>* %p) {
   %v = load <4 x float>, <4 x float>* %p
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32(float* %p) {
+  %e = load float, float* %p
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_folded_offset(<4 x float>* %p) {
   %q = ptrtoint <4 x float>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_with_folded_offset(float* %p) {
+  %q = ptrtoint float* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to float*
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_folded_gep_offset(<4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 4($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_with_folded_gep_offset(float* %p) {
+  %s = getelementptr inbounds float, float* %p, i32 1
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_gep_negative_offset(<4 x float>* %p) {
   %s = getelementptr inbounds <4 x float>, <4 x float>* %p, i32 -1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -4{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_with_unfolded_gep_negative_offset(float* %p) {
+  %s = getelementptr inbounds float, float* %p, i32 -1
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_offset(<4 x float>* %p) {
   %q = ptrtoint <4 x float>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_with_unfolded_offset(float* %p) {
+  %q = ptrtoint float* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to float*
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_with_unfolded_gep_offset(<4 x float>* %p) {
   %s = getelementptr <4 x float>, <4 x float>* %p, i32 1
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 4{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_with_unfolded_gep_offset(float* %p) {
+  %s = getelementptr float, float* %p, i32 1
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @load_v4f32_from_numeric_address() {
   %s = inttoptr i32 32 to <4 x float>*
   %v = load <4 x float>, <4 x float>* %s
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @load_splat_v4f32_from_numeric_address() {
+  %s = inttoptr i32 32 to float*
+  %e = load float, float* %s
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: load_v4f32_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype load_v4f32_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v4f32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v4f32 = global <4 x float> <float 42., float 42., float 42., float 42.>
 define <4 x float> @load_v4f32_from_global_address() {
   %v = load <4 x float>, <4 x float>* @gv_v4f32
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: load_splat_v4f32_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v4f32_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, gv_f32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_f32 = global float 42.
+define <4 x float> @load_splat_v4f32_from_global_address() {
+  %e = load float, float* @gv_f32
+  %v1 = insertelement <4 x float> undef, float %e, i32 0
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %v2
+}
+
 ; CHECK-LABEL: store_v4f32:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .functype store_v4f32 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v4f32(<4 x float> %v, <4 x float>* %p) {
   store <4 x float> %v , <4 x float>* %p
   ret void
 }

 ; SIMD128-NEXT: .functype load_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64(<2 x double>* %p) {
   %v = load <2 x double>, <2 x double>* %p
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64 (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64(double* %p) {
+  %e = load double, double* %p
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_with_folded_offset(double* %p) {
+  %q = ptrtoint double* %p to i32
+  %r = add nuw i32 %q, 16
+  %s = inttoptr i32 %r to double*
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_gep_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_with_folded_gep_offset(double* %p) {
+  %s = getelementptr inbounds double, double* %p, i32 1
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_negative_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_with_unfolded_gep_negative_offset(double* %p) {
+  %s = getelementptr inbounds double, double* %p, i32 -1
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_with_unfolded_offset(double* %p) {
+  %q = ptrtoint double* %p to i32
+  %r = add nsw i32 %q, 16
+  %s = inttoptr i32 %r to double*
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_offset(<2 x double>* %p) {
   %s = getelementptr <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_with_unfolded_gep_offset(double* %p) {
+  %s = getelementptr double, double* %p, i32 1
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @load_splat_v2f64_from_numeric_address() {
+  %s = inttoptr i32 32 to double*
+  %e = load double, double* %s
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: load_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2f64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2f64 = global <2 x double> <double 42., double 42.>
 define <2 x double> @load_v2f64_from_global_address() {
   %v = load <2 x double>, <2 x double>* @gv_v2f64
   ret <2 x double> %v
 }
 
+; CHECK-LABEL: load_splat_v2f64_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_splat_v2f64_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_f64($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+@gv_f64 = global double 42.
+define <2 x double> @load_splat_v2f64_from_global_address() {
+  %e = load double, double* @gv_f64
+  %v1 = insertelement <2 x double> undef, double %e, i32 0
+  %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
+  ret <2 x double> %v2
+}
+
 ; CHECK-LABEL: store_v2f64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2f64(<2 x double> %v, <2 x double>* %p) {
   store <2 x double> %v , <2 x double>* %p
   ret void

llvm/trunk/test/MC/WebAssembly/simd-encodings.s

main:
     f32x4.convert_i32x4_u
 
     # CHECK: f64x2.convert_i64x2_s # encoding: [0xfd,0xb1,0x01]
     f64x2.convert_i64x2_s
 
     # CHECK: f64x2.convert_i64x2_u # encoding: [0xfd,0xb2,0x01]
     f64x2.convert_i64x2_u
 
+    # CHECK: v8x16.load_splat 48 # encoding: [0xfd,0xc2,0x01,0x00,0x30]
+    v8x16.load_splat 48
+
+    # CHECK: v16x8.load_splat 48 # encoding: [0xfd,0xc3,0x01,0x01,0x30]
+    v16x8.load_splat 48
+
+    # CHECK: v32x4.load_splat 48 # encoding: [0xfd,0xc4,0x01,0x02,0x30]
+    v32x4.load_splat 48
+
+    # CHECK: v64x2.load_splat 48 # encoding: [0xfd,0xc5,0x01,0x03,0x30]
+    v64x2.load_splat 48
+
     # CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0xc6,0x01]
     i8x16.narrow_i16x8_s
 
     # CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0xc7,0x01]
     i8x16.narrow_i16x8_u
 
     # CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0xc8,0x01]
     i16x8.narrow_i32x4_s