[ARM] Fix CTTZ for MVE

[oliverlars]

Summary

CTTZ was set to Expand instead of Custom so it output the wrong instructions.

[dmgreen]

Righteo, LGTM.

[oliverlars]

r372401

llvm/lib/Target/ARM/ARMISelLowering.cpp

for (auto VT : IntTypes) {
     setOperationAction(ISD::SMAX, VT, Legal);
     setOperationAction(ISD::UMIN, VT, Legal);
     setOperationAction(ISD::UMAX, VT, Legal);
     setOperationAction(ISD::ABS, VT, Legal);
     setOperationAction(ISD::SETCC, VT, Custom);
     setOperationAction(ISD::MLOAD, VT, Custom);
     setOperationAction(ISD::MSTORE, VT, Legal);
     setOperationAction(ISD::CTLZ, VT, Legal);
-    setOperationAction(ISD::CTTZ, VT, Expand);
+    setOperationAction(ISD::CTTZ, VT, Custom);
     setOperationAction(ISD::BITREVERSE, VT, Legal);
     setOperationAction(ISD::BSWAP, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);
     setOperationAction(ISD::SDIV, VT, Expand);
     setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SREM, VT, Expand);

llvm/test/CodeGen/Thumb2/mve-cttz.ll

 entry:
   %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){
 ; CHECK-LABEL: cttz_4i32_0_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i32 q1, #0x1
-; CHECK-NEXT:    vsub.i32 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i32 q1, #0x20
+; CHECK-NEXT:    movs r0, #32
+; CHECK-NEXT:    vbrsr.32 q0, q0, r0
 ; CHECK-NEXT:    vclz.i32 q0, q0
-; CHECK-NEXT:    vsub.i32 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 0)
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_0_t(<8 x i16> %src){
 ; CHECK-LABEL: cttz_8i16_0_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i16 q1, #0x1
-; CHECK-NEXT:    vsub.i16 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i16 q1, #0x10
+; CHECK-NEXT:    movs r0, #16
+; CHECK-NEXT:    vbrsr.16 q0, q0, r0
 ; CHECK-NEXT:    vclz.i16 q0, q0
-; CHECK-NEXT:    vsub.i16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 0)
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_0_t(<16 x i8> %src) {
 ; CHECK-LABEL: cttz_16i8_0_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i8 q1, #0x1
-; CHECK-NEXT:    vsub.i8 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i8 q1, #0x8
+; CHECK-NEXT:    movs r0, #8
+; CHECK-NEXT:    vbrsr.8 q0, q0, r0
 ; CHECK-NEXT:    vclz.i8 q0, q0
-; CHECK-NEXT:    vsub.i8 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0)
   ret <16 x i8> %0
 }
 
 define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){
 ; CHECK-LABEL: cttz_2i64_1_t:

 entry:
   %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){
 ; CHECK-LABEL: cttz_4i32_1_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i32 q1, #0x1
-; CHECK-NEXT:    vsub.i32 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i32 q1, #0x20
+; CHECK-NEXT:    movs r0, #32
+; CHECK-NEXT:    vbrsr.32 q0, q0, r0
 ; CHECK-NEXT:    vclz.i32 q0, q0
-; CHECK-NEXT:    vsub.i32 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 1)
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_1_t(<8 x i16> %src){
 ; CHECK-LABEL: cttz_8i16_1_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i16 q1, #0x1
-; CHECK-NEXT:    vsub.i16 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i16 q1, #0x10
+; CHECK-NEXT:    movs r0, #16
+; CHECK-NEXT:    vbrsr.16 q0, q0, r0
 ; CHECK-NEXT:    vclz.i16 q0, q0
-; CHECK-NEXT:    vsub.i16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 1)
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_1_t(<16 x i8> %src) {
 ; CHECK-LABEL: cttz_16i8_1_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.i8 q1, #0x1
-; CHECK-NEXT:    vsub.i8 q1, q0, q1
-; CHECK-NEXT:    vbic q0, q1, q0
-; CHECK-NEXT:    vmov.i8 q1, #0x8
+; CHECK-NEXT:    movs r0, #8
+; CHECK-NEXT:    vbrsr.8 q0, q0, r0
 ; CHECK-NEXT:    vclz.i8 q0, q0
-; CHECK-NEXT:    vsub.i8 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 1)
   ret <16 x i8> %0
 }
 
 
 declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
 declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
 declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
 declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)