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[MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.
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Authored by eugenis on Sep 18 2019, 4:57 PM.

Event Timeline

eugenis created this revision.Sep 18 2019, 4:57 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 18 2019, 4:57 PM
ostannard added inline comments.Sep 19 2019, 2:50 AM
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
211

STZG and STZ2G store zero to the memory contents, so don't belong in this list according to the comment above. After reading the rest of the patch, I think it's the comment that's wrong, these instructions are allowed to write regular memory, but not with contents which depend on the address part of the input register.

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir
4

We should also test a mis-aligned offset (e.g. $x0 = ADDXri $x0, 8, 0) as well as the edges of the range.

eugenis updated this revision to Diff 220908.Sep 19 2019, 1:51 PM
eugenis marked 2 inline comments as done.

Added merging of STGP with the same source and address register.
Added more tests.
Fixed a comment.

eugenis added a comment.EditedSep 19 2019, 1:53 PM

I've noticed that the spec does not say that STGP with the same source and address register is unpredictable, and instead defines it to update the writeback register after the source register is read. This lets us merge STGP forward, but not backward. Implemented with tests.

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
211

Good point! Reworded the comment.

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir
4

Added a test for mis-aligned offset. What do you mean by the edges of the range? There are tests for extreme values of the offset in ADDXri, see test_STG_post2 .. test_STG_post5 below and the same for STGP.

ostannard accepted this revision.Sep 20 2019, 2:36 AM

LGTM

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir
4

I meant the extreme values which you already have tests for.

This revision is now accepted and ready to land.Sep 20 2019, 2:36 AM
This revision was automatically updated to reflect the committed changes.