[ARM] SBFX from rsb patterns

[dmgreen]

Summary

Sometimes ISel will generate RSB patterns for sequences that should be transformed into sbfx, instead of the usual shifts, and we end up generating a RSB and a UBFX. This adds some extra patterns to catch the other cases. The existing sbfx patterns are selected through ARMDAGToDAGISel::tryV6T2BitfieldExtractOp, but these tablegen patterns seem to work for these cases just fine. Helps especially in the MVE predication code.

[efriedma]

Would it make sense to try to canonicalize this to shl+ashr at the IR level?

[dmgreen]

Hello

That wouldn't help the MVE predicate case, which is what i was really after here. It is coming from a insert_vector_elt(extract_vector_elt(..)), where we generate a sign_extend_inreg, which is legalised to the rsb and the and. D67956 contains an alternative where we lower that using a LSL, SRA pair instead, which will then transform to the SBFX as desired.

I didn't see any other cases of this coming up in the tests I ran, so that alternative might be the simpler approach.

llvm/lib/Target/ARM/ARMInstrThumb2.td

def t2SBFX: T2TwoRegBitFI<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
                  IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-20} = 0b10100;
   let Inst{15} = 0;
 }
 
+// sub(0, and(shr(x, C), 1)) == SBFX(x, C, 1)
+// The shr can be sra or srl, or be not present (in which case shift is 0)
+// The last parameter ($msb) is really width-1, so 0.
+def : T2Pat<(sub (i32 0), (and rGPR:$Rn, (i32 1))),
+            (t2SBFX $Rn, (i32 0), (i32 0))>;
+def : T2Pat<(sub (i32 0), (and (srl rGPR:$Rn, (i32 imm:$C)), (i32 1))),
+            (t2SBFX $Rn, (i32 imm:$C), (i32 0))>;
+def : T2Pat<(sub (i32 0), (and (sra rGPR:$Rn, (i32 imm:$C)), (i32 1))),
+            (t2SBFX $Rn, (i32 imm:$C), (i32 0))>;
+
 def t2UBFX: T2TwoRegBitFI<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
                  IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-20} = 0b11100;
   let Inst{15} = 0;
 }

llvm/test/CodeGen/ARM/sbfx.ll

; CHECK-NEXT:    bx lr
   %tmp = lshr i32 %a, 25
   %res = trunc i32 %tmp to i8
   ret i8 %res
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_rsb(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %b = lshr i32 %a, 4
   %c = and i32 %b, 1
   %d = sub i32 0, %c
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_rsb1(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    ubfx r0, r0, #4, #1
 ; CHECK-NEXT:    rsb r0, r0, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %b = lshr i32 %a, 4
   %c = and i32 %b, 1
   %d = sub i32 1, %c
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_rsb_and(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb_and:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = and i32 %a, 1
   %d = sub i32 0, %c
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_shift31(i32 %a) {
 ; CHECK-LABEL: sbfx_shift31:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %ba = lshr i32 %a, 4
   %ca = shl i32 %ba, 31
   %d = ashr i32 %ca, 31
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_shift30(i32 %a) {
 ; CHECK-LABEL: sbfx_shift30:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    sbfx r0, r0, #4, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %ba = lshr i32 %a, 4
   %ca = shl i32 %ba, 30
   %d = ashr i32 %ca, 30
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_trunci1(i32 %a) {
 ; CHECK-LABEL: sbfx_trunci1:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %t1 = lshr i32 %a, 4
   %t2 = trunc i32 %t1 to i1
   %t3 = sext i1 %t2 to i32
   ret i32 %t3
 }
 

llvm/test/CodeGen/Thumb2/bfx.ll

; CHECK-NEXT:    bx lr
   %t1 = lshr i32 %a, 7
   %t2 = and i32 %t1, 2047
   ret i32 %t2
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_rsb(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %b = lshr i32 %a, 4
   %c = and i32 %b, 1
   %d = sub i32 0, %c
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_shift(i32 %a) {
 ; CHECK-LABEL: sbfx_shift:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %ba = lshr i32 %a, 4
   %ca = shl i32 %ba, 31
   %d = ashr i32 %ca, 31
   ret i32 %d
 }
 
 define arm_aapcs_vfpcc i32 @sbfx_trunci1(i32 %a) {
 ; CHECK-LABEL: sbfx_trunci1:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %t1 = lshr i32 %a, 4
   %t2 = trunc i32 %t1 to i1
   %t3 = sext i1 %t2 to i32
   ret i32 %t3
 }

llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

 define void @foo_sext_v4i32_v4i8(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i8> *%src) {
 ; CHECK-LABEL: foo_sext_v4i32_v4i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrbne r3, [r2]
 ; CHECK-NEXT:    vmovne.32 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    ldrbmi r3, [r2, #1]

 define void @foo_sext_v4i32_v4i16(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i16> *%src) {
 ; CHECK-LABEL: foo_sext_v4i32_v4i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrhne r3, [r2]
 ; CHECK-NEXT:    vmovne.32 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    ldrhmi r3, [r2, #2]

 define void @foo_zext_v4i32_v4i8(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i8> *%src) {
 ; CHECK-LABEL: foo_zext_v4i32_v4i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vmov.i32 q1, #0xff
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrbne r3, [r2]
 ; CHECK-NEXT:    vmovne.32 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    ldrbmi r3, [r2, #1]

 define void @foo_zext_v4i32_v4i16(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i16> *%src) {
 ; CHECK-LABEL: foo_zext_v4i32_v4i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrhne r3, [r2]
 ; CHECK-NEXT:    vmovne.32 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    ldrhmi r3, [r2, #2]

 define void @foo_sext_v8i16_v8i8(<8 x i16> *%dest, <8 x i16> *%mask, <8 x i8> *%src) {
 ; CHECK-LABEL: foo_sext_v8i16_v8i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r3, lr, #1
-; CHECK-NEXT:    ubfx r1, lr, #2, #1
-; CHECK-NEXT:    rsb.w r12, r3, #0
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r1, lr, #2, #1
 ; CHECK-NEXT:    bfi r3, r12, #0, #1
 ; CHECK-NEXT:    bfi r3, r1, #1, #1
-; CHECK-NEXT:    ubfx r1, lr, #4, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #4, #1
 ; CHECK-NEXT:    bfi r3, r1, #2, #1
-; CHECK-NEXT:    ubfx r1, lr, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #6, #1
 ; CHECK-NEXT:    bfi r3, r1, #3, #1
-; CHECK-NEXT:    ubfx r1, lr, #8, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #8, #1
 ; CHECK-NEXT:    bfi r3, r1, #4, #1
-; CHECK-NEXT:    ubfx r1, lr, #10, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #10, #1
 ; CHECK-NEXT:    bfi r3, r1, #5, #1
-; CHECK-NEXT:    ubfx r1, lr, #12, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #12, #1
 ; CHECK-NEXT:    bfi r3, r1, #6, #1
-; CHECK-NEXT:    ubfx r1, lr, #14, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #14, #1
 ; CHECK-NEXT:    bfi r3, r1, #7, #1
 ; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    lsls r3, r3, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrbne r3, [r2]
 ; CHECK-NEXT:    vmovne.16 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi

 define void @foo_zext_v8i16_v8i8(<8 x i16> *%dest, <8 x i16> *%mask, <8 x i8> *%src) {
 ; CHECK-LABEL: foo_zext_v8i16_v8i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r3, lr, #1
-; CHECK-NEXT:    ubfx r1, lr, #2, #1
-; CHECK-NEXT:    rsb.w r12, r3, #0
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r1, lr, #2, #1
 ; CHECK-NEXT:    bfi r3, r12, #0, #1
 ; CHECK-NEXT:    bfi r3, r1, #1, #1
-; CHECK-NEXT:    ubfx r1, lr, #4, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #4, #1
 ; CHECK-NEXT:    bfi r3, r1, #2, #1
-; CHECK-NEXT:    ubfx r1, lr, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #6, #1
 ; CHECK-NEXT:    bfi r3, r1, #3, #1
-; CHECK-NEXT:    ubfx r1, lr, #8, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #8, #1
 ; CHECK-NEXT:    bfi r3, r1, #4, #1
-; CHECK-NEXT:    ubfx r1, lr, #10, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #10, #1
 ; CHECK-NEXT:    bfi r3, r1, #5, #1
-; CHECK-NEXT:    ubfx r1, lr, #12, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #12, #1
 ; CHECK-NEXT:    bfi r3, r1, #6, #1
-; CHECK-NEXT:    ubfx r1, lr, #14, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #14, #1
 ; CHECK-NEXT:    bfi r3, r1, #7, #1
 ; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    lsls r3, r3, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    ldrbne r3, [r2]
 ; CHECK-NEXT:    vmovne.16 q0[0], r3
 ; CHECK-NEXT:    lsls r3, r1, #30
 ; CHECK-NEXT:    itt mi

 }
 
 define void @foo_trunc_v8i8_v8i16(<8 x i8> *%dest, <8 x i16> *%mask, <8 x i16> *%src) {
 ; CHECK-LABEL: foo_trunc_v8i8_v8i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrht.u16 q0, [r2]
 ; CHECK-NEXT:    vmrs r1, p0
-; CHECK-NEXT:    and r2, r1, #1
-; CHECK-NEXT:    rsbs r3, r2, #0
-; CHECK-NEXT:    movs r2, #0
-; CHECK-NEXT:    bfi r2, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r1, #2, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r1, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, r1, #6, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #3, #1
-; CHECK-NEXT:    ubfx r3, r1, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #4, #1
-; CHECK-NEXT:    ubfx r3, r1, #10, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #5, #1
-; CHECK-NEXT:    ubfx r3, r1, #12, #1
-; CHECK-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
-; CHECK-NEXT:    bfi r2, r1, #7, #1
-; CHECK-NEXT:    uxtb r1, r2
-; CHECK-NEXT:    lsls r2, r2, #31
+; CHECK-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-NEXT:    bfi r3, r2, #0, #1
+; CHECK-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-NEXT:    bfi r3, r2, #1, #1
+; CHECK-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-NEXT:    bfi r3, r2, #2, #1
+; CHECK-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-NEXT:    bfi r3, r2, #3, #1
+; CHECK-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-NEXT:    bfi r3, r2, #4, #1
+; CHECK-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-NEXT:    bfi r3, r2, #5, #1
+; CHECK-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-NEXT:    bfi r3, r2, #6, #1
+; CHECK-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-NEXT:    bfi r3, r1, #7, #1
+; CHECK-NEXT:    lsls r2, r3, #31
+; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    vmovne.u16 r2, q0[0]
 ; CHECK-NEXT:    strbne r2, [r0]
 ; CHECK-NEXT:    lsls r2, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    vmovmi.u16 r2, q0[1]
 ; CHECK-NEXT:    strbmi r2, [r0, #1]
 ; CHECK-NEXT:    lsls r2, r1, #29

 }
 
 define void @foo_trunc_v4i8_v4i32(<4 x i8> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
 ; CHECK-LABEL: foo_trunc_v4i8_v4i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q0, [r2]
 ; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r1, r2, #1
-; CHECK-NEXT:    rsbs r3, r1, #0
-; CHECK-NEXT:    movs r1, #0
+; CHECK-NEXT:    sbfx r3, r2, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #4, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-NEXT:    ubfx r2, r2, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sbfx r2, r2, #12, #1
 ; CHECK-NEXT:    bfi r1, r2, #3, #1
 ; CHECK-NEXT:    lsls r2, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    vmovne r2, s0
 ; CHECK-NEXT:    strbne r2, [r0]
 ; CHECK-NEXT:    lsls r2, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    vmovmi r2, s1

 }
 
 define void @foo_trunc_v4i16_v4i32(<4 x i16> *%dest, <4 x i32> *%mask, <4 x i32> *%src) {
 ; CHECK-LABEL: foo_trunc_v4i16_v4i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q0, [r2]
 ; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r1, r2, #1
-; CHECK-NEXT:    rsbs r3, r1, #0
-; CHECK-NEXT:    movs r1, #0
+; CHECK-NEXT:    sbfx r3, r2, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #4, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-NEXT:    ubfx r2, r2, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sbfx r2, r2, #12, #1
 ; CHECK-NEXT:    bfi r1, r2, #3, #1
 ; CHECK-NEXT:    lsls r2, r1, #31
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    vmovne r2, s0
 ; CHECK-NEXT:    strhne r2, [r0]
 ; CHECK-NEXT:    lsls r2, r1, #30
 ; CHECK-NEXT:    itt mi
 ; CHECK-NEXT:    vmovmi r2, s1

llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll

 
 
 define arm_aapcs_vfpcc i4 @bitcast_from_v4i1(<4 x i32> %a) {
 ; CHECK-LE-LABEL: bitcast_from_v4i1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    .pad #4
 ; CHECK-LE-NEXT:    sub sp, #4
 ; CHECK-LE-NEXT:    vcmp.i32 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r0, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r0, #0
 ; CHECK-LE-NEXT:    movs r0, #0
+; CHECK-LE-NEXT:    vmrs r1, p0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
+; CHECK-LE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-LE-NEXT:    bfi r0, r1, #3, #1
 ; CHECK-LE-NEXT:    add sp, #4
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: bitcast_from_v4i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .pad #4
 ; CHECK-BE-NEXT:    sub sp, #4
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    movs r0, #0
 ; CHECK-BE-NEXT:    vcmp.i32 eq, q1, zr
 ; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r0, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r0, #0
-; CHECK-BE-NEXT:    movs r0, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
+; CHECK-BE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-BE-NEXT:    bfi r0, r1, #3, #1
 ; CHECK-BE-NEXT:    add sp, #4
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %c = icmp eq <4 x i32> %a, zeroinitializer
   %b = bitcast <4 x i1> %c to i4
   ret i4 %b
 }
 
 define arm_aapcs_vfpcc i8 @bitcast_from_v8i1(<8 x i16> %a) {
 ; CHECK-LE-LABEL: bitcast_from_v8i1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    .pad #8
 ; CHECK-LE-NEXT:    sub sp, #8
 ; CHECK-LE-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r0, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r0, #0
-; CHECK-LE-NEXT:    movs r0, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #2, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #6, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #3, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #4, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #10, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #5, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #12, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #6, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
-; CHECK-LE-NEXT:    bfi r0, r1, #7, #1
-; CHECK-LE-NEXT:    uxtb r0, r0
+; CHECK-LE-NEXT:    movs r2, #0
+; CHECK-LE-NEXT:    vmrs r0, p0
+; CHECK-LE-NEXT:    sbfx r1, r0, #0, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #0, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #2, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #1, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #4, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #2, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #6, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #3, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #8, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #4, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #10, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #5, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #12, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #6, #1
+; CHECK-LE-NEXT:    sbfx r0, r0, #14, #1
+; CHECK-LE-NEXT:    bfi r2, r0, #7, #1
+; CHECK-LE-NEXT:    uxtb r0, r2
 ; CHECK-LE-NEXT:    add sp, #8
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: bitcast_from_v8i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .pad #8
 ; CHECK-BE-NEXT:    sub sp, #8
 ; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    movs r2, #0
 ; CHECK-BE-NEXT:    vcmp.i16 eq, q1, zr
-; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r0, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r0, #0
-; CHECK-BE-NEXT:    movs r0, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #2, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #6, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #3, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #4, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #10, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #5, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #12, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #6, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
-; CHECK-BE-NEXT:    bfi r0, r1, #7, #1
-; CHECK-BE-NEXT:    uxtb r0, r0
+; CHECK-BE-NEXT:    vmrs r0, p0
+; CHECK-BE-NEXT:    sbfx r1, r0, #0, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #0, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #2, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #1, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #4, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #2, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #6, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #3, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #8, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #4, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #10, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #5, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #12, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #6, #1
+; CHECK-BE-NEXT:    sbfx r0, r0, #14, #1
+; CHECK-BE-NEXT:    bfi r2, r0, #7, #1
+; CHECK-BE-NEXT:    uxtb r0, r2
 ; CHECK-BE-NEXT:    add sp, #8
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %a, zeroinitializer
   %b = bitcast <8 x i1> %c to i8
   ret i8 %b
 }
 

llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
 
 
 define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: build_var0_v4i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #4
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 0
   %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %r
 }
 
 define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: build_var3_v4i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #12, #4
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 3
   %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %r
 }
 
 define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: build_varN_v4i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #4
 ; CHECK-NEXT:    bfi r1, r0, #4, #4
 ; CHECK-NEXT:    bfi r1, r0, #8, #4
 ; CHECK-NEXT:    bfi r1, r0, #12, #4
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc1 = insertelement <4 x i1> undef, i1 %c, i64 0
   %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer
   %r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %r
 }
 
 
 define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: build_var0_v8i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #2
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 0
   %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %r
 }
 
 define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: build_var3_v8i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #6, #2
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 3
   %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %r
 }
 
 define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: build_varN_v8i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #2
 ; CHECK-NEXT:    bfi r1, r0, #2, #2
 ; CHECK-NEXT:    bfi r1, r0, #4, #2
 ; CHECK-NEXT:    bfi r1, r0, #6, #2
 ; CHECK-NEXT:    bfi r1, r0, #8, #2
 ; CHECK-NEXT:    bfi r1, r0, #10, #2
 ; CHECK-NEXT:    bfi r1, r0, #12, #2
 ; CHECK-NEXT:    bfi r1, r0, #14, #2

 
 
 define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: build_var0_v16i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #1
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0
   %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
   ret <16 x i8> %r
 }
 
 define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: build_var3_v16i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #3, #1
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3
   %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
   ret <16 x i8> %r
 }
 
 define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: build_varN_v16i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #1, #1
 ; CHECK-NEXT:    bfi r1, r0, #2, #1
 ; CHECK-NEXT:    bfi r1, r0, #3, #1
 ; CHECK-NEXT:    bfi r1, r0, #4, #1
 ; CHECK-NEXT:    bfi r1, r0, #5, #1
 ; CHECK-NEXT:    bfi r1, r0, #6, #1
 ; CHECK-NEXT:    bfi r1, r0, #7, #1

 }
 
 
 define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: build_var0_v2i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov s8, r0
 ; CHECK-NEXT:    vldr s10, .LCPI9_0
 ; CHECK-NEXT:    vmov.f32 s9, s8
 ; CHECK-NEXT:    vmov.f32 s11, s10
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vorr q0, q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI9_0:
 ; CHECK-NEXT:    .long 0 @ float 0
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0
   %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %r
 }
 
 define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: build_var1_v2i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov s10, r0
 ; CHECK-NEXT:    vldr s8, .LCPI10_0
 ; CHECK-NEXT:    vmov.f32 s9, s8
 ; CHECK-NEXT:    vmov.f32 s11, s10
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vorr q0, q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI10_0:
 ; CHECK-NEXT:    .long 0 @ float 0
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1
   %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %r
 }
 
 define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: build_varN_v2i1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vdup.32 q2, r0
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vorr q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = icmp ult i32 %s, %t
   %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0
   %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer
   %r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %r
 }

llvm/test/CodeGen/Thumb2/mve-pred-ext.ll

entry:
   ret <16 x i8> %1
 }
 
 define arm_aapcs_vfpcc <2 x i64> @trunc_v2i1_v2i64(<2 x i64> %src) {
 ; CHECK-LABEL: trunc_v2i1_v2i64:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov r1, s0
 ; CHECK-NEXT:    vmov r0, s2
-; CHECK-NEXT:    and r1, r1, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
-; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    sbfx r1, r1, #0, #1
 ; CHECK-NEXT:    vmov.32 q1[0], r1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov.32 q1[1], r1
 ; CHECK-NEXT:    vmov.32 q1[2], r0
 ; CHECK-NEXT:    vmov.32 q1[3], r0
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = trunc <2 x i64> %src to <2 x i1>
   %1 = select <2 x i1> %0, <2 x i64> %src, <2 x i64> zeroinitializer

llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll

 
 
 define arm_aapcs_vfpcc void @store_v4i1(<4 x i1> *%dst, <4 x i32> %a) {
 ; CHECK-LE-LABEL: store_v4i1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    vcmp.i32 eq, q0, zr
 ; CHECK-LE-NEXT:    movs r3, #0
 ; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r2, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
+; CHECK-LE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-LE-NEXT:    bfi r3, r1, #3, #1
 ; CHECK-LE-NEXT:    strb r3, [r0]
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: store_v4i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
 ; CHECK-BE-NEXT:    movs r3, #0
 ; CHECK-BE-NEXT:    vcmp.i32 eq, q1, zr
 ; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r2, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
+; CHECK-BE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-BE-NEXT:    bfi r3, r1, #3, #1
 ; CHECK-BE-NEXT:    strb r3, [r0]
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %c = icmp eq <4 x i32> %a, zeroinitializer
   store <4 x i1> %c, <4 x i1>* %dst
   ret void
 }
 
 define arm_aapcs_vfpcc void @store_v8i1(<8 x i1> *%dst, <8 x i16> %a) {
 ; CHECK-LE-LABEL: store_v8i1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r2, p0
-; CHECK-LE-NEXT:    and r1, r2, #1
-; CHECK-LE-NEXT:    rsbs r3, r1, #0
-; CHECK-LE-NEXT:    movs r1, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #0, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #1, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #2, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #6, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #3, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #4, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #10, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #5, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #12, #1
-; CHECK-LE-NEXT:    ubfx r2, r2, #14, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #6, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r1, r2, #7, #1
-; CHECK-LE-NEXT:    strb r1, [r0]
+; CHECK-LE-NEXT:    movs r3, #0
+; CHECK-LE-NEXT:    vmrs r1, p0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #0, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #1, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #2, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #3, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #4, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #5, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #6, #1
+; CHECK-LE-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-LE-NEXT:    bfi r3, r1, #7, #1
+; CHECK-LE-NEXT:    strb r3, [r0]
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: store_v8i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    movs r3, #0
 ; CHECK-BE-NEXT:    vcmp.i16 eq, q1, zr
-; CHECK-BE-NEXT:    vmrs r2, p0
-; CHECK-BE-NEXT:    and r1, r2, #1
-; CHECK-BE-NEXT:    rsbs r3, r1, #0
-; CHECK-BE-NEXT:    movs r1, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #0, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #1, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #2, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #6, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #3, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #4, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #10, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #5, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #12, #1
-; CHECK-BE-NEXT:    ubfx r2, r2, #14, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #6, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r1, r2, #7, #1
-; CHECK-BE-NEXT:    strb r1, [r0]
+; CHECK-BE-NEXT:    vmrs r1, p0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #0, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #1, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #2, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #3, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #4, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #5, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #6, #1
+; CHECK-BE-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-BE-NEXT:    bfi r3, r1, #7, #1
+; CHECK-BE-NEXT:    strb r3, [r0]
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %a, zeroinitializer
   store <8 x i1> %c, <8 x i1>* %dst
   ret void
 }
 
 define arm_aapcs_vfpcc void @store_v16i1(<16 x i1> *%dst, <16 x i8> %a) {