[ARM][LowOverheadLoops] Add LR def safety check

[samparker]

Summary

Converting the *LoopStart pseudo instructions into DLS/WLS results in LR being defined. These instructions were inserted on the assumption that LR would already contain the loop counter because a mov is introduced during ISel as the the consumers in the loop can only use LR. That assumption proved wrong! So perform a safety check, finding an appropriate place to insert the DLS/WLS instructions or revert if this isn't possible.

Almost all the tests have changed because liveness tracking is enabled.

[dmgreen]

Will tracking liveness this late be OK? I have a memory of it not being reliable, but that might have been fixed up recently?

And it seems a little odd that the t2DoLoopStart/t2WhileLoopStart wouldn't have any reference to LR in it! But that's what it is. Lets get this problem fixed first.

lib/Target/ARM/ARMLowOverheadLoops.cpp

122 ↗

(On Diff #220052)

Can this be something like for(auto MI : make_range(T(Begin), End)) ?

155 ↗

(On Diff #220052)

Is this always just a tMOVr? Would it be better to check that specifically?

169 ↗

(On Diff #220052)

Is the template type needed, or can it be left implicit?

182 ↗

(On Diff #220052)

To > Do this

[samparker]

For the liveness used here, it's just based upon collecting the live ins from the successor blocks and I though that was okay. Thanks for the iterator suggestions, I'll look into them.

lib/Target/ARM/ARMLowOverheadLoops.cpp

155 ↗

(On Diff #220052)

sounds good.

[samparker]

• Removed the template from SearchUse as we only use it once.
• Updated the searches to iterate over a range.
• Tried to see if the iterator kind, for SearchDef, could be implicit, but I didn't find a way to have a generic 'iterator' for the machine block - one without its direction defined.

[dmgreen]

LGTM. Thanks.

lib/Target/ARM/ARMLowOverheadLoops.cpp

169 ↗

(On Diff #220052)

I meant can it just be: MachineInstr *PredLRDef =SearchForDef(Start, MBB->rend(), ARM::LR), and it picks up the reverse_iterator automatically from the rend type. So SearchForDef is the same template, it's just that the template type is implicit from the args. I'm not sure if this will work or not (or if it's actually better!)

[samparker]

lib/Target/ARM/ARMLowOverheadLoops.cpp

169 ↗

(On Diff #220052)

Well every day is a school day - I didn't know that was a thing! Will change before committing. Thanks!

[RKSimon]

@samparker I think your recent commits are causing failures on EXPENSIVE_CHECKS builds, please can you take a look?
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19705/steps/test-check-all/logs/stdio

Failing Tests (20):
    LLVM :: CodeGen/ARM/2011-12-19-sjlj-clobber.ll
    LLVM :: CodeGen/ARM/constant-island-movwt.mir
    LLVM :: CodeGen/ARM/constant-islands-cfg.mir
    LLVM :: CodeGen/ARM/constant-islands-split-IT.mir
    LLVM :: CodeGen/ARM/fp16-litpool-arm.mir
    LLVM :: CodeGen/ARM/fp16-litpool-thumb.mir
    LLVM :: CodeGen/ARM/jump-table-islands.ll
    LLVM :: CodeGen/ARM/space-directive.ll
    LLVM :: CodeGen/ARM/thumb-big-stack.ll
    LLVM :: CodeGen/ARM/v8m.base-jumptable_alignment.ll
    LLVM :: CodeGen/Thumb/pr42760.ll
    LLVM :: CodeGen/Thumb2/LowOverheadLoops/massive.mir
    LLVM :: CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
    LLVM :: CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
    LLVM :: CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
    LLVM :: CodeGen/Thumb2/LowOverheadLoops/switch.mir
    LLVM :: CodeGen/Thumb2/constant-islands-new-island.ll
    LLVM :: CodeGen/Thumb2/constant-islands.ll
    LLVM :: CodeGen/Thumb2/large-call.ll
    LLVM :: CodeGen/Thumb2/thumb2-tbh.ll

[krasimir]

@samparker : right after r372126 there still seems to be a test failure remaining:

; CHECK-NEXT: Machine Natural Loop Construction
              ^
<stdin>:156:2: note: 'next' match was here
 Machine Natural Loop Construction
 ^
<stdin>:154:58: note: previous match ended here
 ARM constant island placement and branch shortening pass
                                                         ^
<stdin>:155:1: note: non-matching line after previous match is here
 MachineDominator Tree Construction
^

--

********************
Testing Time: 96.32s
********************
Failing Tests (1):
    LLVM :: CodeGen/ARM/O3-pipeline.ll

  Expected Passes    : 32993
  Expected Failures  : 147
  Unsupported Tests  : 433
  Unexpected Failures: 1
FAILED: test/CMakeFiles/check-llvm

[dmgreen]

Hello. Yes, that should all be fixed now. Let us know if anything else is looking off.

[RKSimon]

In D67539#1672913, @dmgreen wrote:

Hello. Yes, that should all be fixed now. Let us know if anything else is looking off.

@samparker @dmgreen CodeGen/Thumb2/LowOverheadLoops/massive.mir is still failing on EXPENSIVE_CHECKS builds - please can you take a look?

[samparker]

@RKSimon Sorry! Should now be done in rL372303.

llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "arm-low-overhead-loops"
 #define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"
 
 namespace {
 
   class ARMLowOverheadLoops : public MachineFunctionPass {
+    MachineFunction           *MF = nullptr;
     const ARMBaseInstrInfo    *TII = nullptr;
     MachineRegisterInfo       *MRI = nullptr;
     std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
 
   public:
     static char ID;
 
     ARMLowOverheadLoops() : MachineFunctionPass(ID) { }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       AU.addRequired<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::NoVRegs);
+    }
+
+    StringRef getPassName() const override {
+      return ARM_LOW_OVERHEAD_LOOPS_NAME;
+    }
+
+  private:
     bool ProcessLoop(MachineLoop *ML);
 
-    bool RevertNonLoops(MachineFunction &MF);
+    MachineInstr * IsSafeToDefineLR(MachineInstr *MI);
+
+    bool RevertNonLoops();
 
     void RevertWhile(MachineInstr *MI) const;
 
     void RevertLoopDec(MachineInstr *MI) const;
 
     void RevertLoopEnd(MachineInstr *MI) const;
 
     void Expand(MachineLoop *ML, MachineInstr *Start,
-                MachineInstr *Dec, MachineInstr *End, bool Revert);
-
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
-    }
+                MachineInstr *InsertPt, MachineInstr *Dec,
+                MachineInstr *End, bool Revert);
 
-    StringRef getPassName() const override {
-      return ARM_LOW_OVERHEAD_LOOPS_NAME;
-    }
   };
 }
 
 char ARMLowOverheadLoops::ID = 0;
 
 INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,
                 false, false)
 
-bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &MF) {
-  if (!static_cast<const ARMSubtarget&>(MF.getSubtarget()).hasLOB())
+bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
+  const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget());
+  if (!ST.hasLOB())
     return false;
 
-  LLVM_DEBUG(dbgs() << "ARM Loops on " << MF.getName() << " ------------- \n");
+  MF = &mf;
+  LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");
 
   auto &MLI = getAnalysis<MachineLoopInfo>();
-  MRI = &MF.getRegInfo();
-  TII = static_cast<const ARMBaseInstrInfo*>(
-    MF.getSubtarget().getInstrInfo());
-  BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF));
+  MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
+  MRI = &MF->getRegInfo();
+  TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
+  BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(*MF));
   BBUtils->computeAllBlockSizes();
-  BBUtils->adjustBBOffsetsAfter(&MF.front());
+  BBUtils->adjustBBOffsetsAfter(&MF->front());
 
   bool Changed = false;
   for (auto ML : MLI) {
     if (!ML->getParentLoop())
       Changed |= ProcessLoop(ML);
   }
-  Changed |= RevertNonLoops(MF);
+  Changed |= RevertNonLoops();
   return Changed;
 }
 
 static bool IsLoopStart(MachineInstr &MI) {
   return MI.getOpcode() == ARM::t2DoLoopStart ||
          MI.getOpcode() == ARM::t2WhileLoopStart;
 }
 
+template<typename T>
+static MachineInstr* SearchForDef(MachineInstr *Begin, T End, unsigned Reg) {
+  for(auto &MI : make_range(T(Begin), End)) {
+    for (auto &MO : MI.operands()) {
+      if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
+        continue;
+      return &MI;
+    }
+  }
+  return nullptr;
+}
+
+static MachineInstr* SearchForUse(MachineInstr *Begin,
+                                  MachineBasicBlock::iterator End,
+                                  unsigned Reg) {
+  for(auto &MI : make_range(MachineBasicBlock::iterator(Begin), End)) {
+    for (auto &MO : MI.operands()) {
+      if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
+        continue;
+      return &MI;
+    }
+  }
+  return nullptr;
+}
+
+// Is it safe to define LR with DLS/WLS?
+// LR can defined if it is the operand to start, because it's the same value,
+// or if it's going to be equivalent to the operand to Start.
+MachineInstr *ARMLowOverheadLoops::IsSafeToDefineLR(MachineInstr *Start) {
+
+  auto IsMoveLR = [](MachineInstr *MI, unsigned Reg) {
+    return MI->getOpcode() == ARM::tMOVr &&
+           MI->getOperand(0).getReg() == ARM::LR &&
+           MI->getOperand(1).getReg() == Reg &&
+           MI->getOperand(2).getImm() == ARMCC::AL;
+   };
+
+  MachineBasicBlock *MBB = Start->getParent();
+  unsigned CountReg = Start->getOperand(0).getReg();
+  // Walk forward and backward in the block to find the closest instructions
+  // that define LR. Then also filter them out if they're not a mov lr.
+  MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR);
+  if (PredLRDef && !IsMoveLR(PredLRDef, CountReg))
+    PredLRDef = nullptr;
+
+  MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR);
+  if (SuccLRDef && !IsMoveLR(SuccLRDef, CountReg))
+    SuccLRDef = nullptr;
+
+  // We've either found one, two or none mov lr instructions... Now figure out
+  // if they are performing the equilvant mov that the Start instruction will.
+  // Do this by scanning forward and backward to see if there's a def of the
+  // register holding the count value. If we find a suitable def, return it as
+  // the insert point. Later, if InsertPt != Start, then we can remove the
+  // redundant instruction.
+  if (SuccLRDef) {
+    MachineBasicBlock::iterator End(SuccLRDef);
+    if (!SearchForDef(Start, End, CountReg)) {
+      return SuccLRDef;
+    } else
+      SuccLRDef = nullptr;
+  }
+  if (PredLRDef) {
+    MachineBasicBlock::reverse_iterator End(PredLRDef);
+    if (!SearchForDef(Start, End, CountReg)) {
+      return PredLRDef;
+    } else
+      PredLRDef = nullptr;
+  }
+
+  // We can define LR because LR already contains the same value.
+  if (Start->getOperand(0).getReg() == ARM::LR)
+    return Start;
+
+  // We've found no suitable LR def and Start doesn't use LR directly. Can we
+  // just define LR anyway? 
+  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+  LivePhysRegs LiveRegs(*TRI);
+  LiveRegs.addLiveOuts(*MBB);
+
+  // Not if we've haven't found a suitable mov and LR is live out.
+  if (LiveRegs.contains(ARM::LR))
+    return nullptr;
+
+  // If LR is not live out, we can insert the instruction if nothing else
+  // uses LR after it.
+  if (!SearchForUse(Start, MBB->end(), ARM::LR))
+    return Start;
+
+  LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find suitable insertion point for"
+             << " LR\n");
+  return nullptr;
+}
+
 bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
 
   bool Changed = false;
 
   // Process inner loops first.
   for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
     Changed |= ProcessLoop(*I);
 
bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
   for (auto *MBB : reverse(ML->getBlocks())) {
     for (auto &MI : *MBB) {
       if (MI.getOpcode() == ARM::t2LoopDec)
         Dec = &MI;
       else if (MI.getOpcode() == ARM::t2LoopEnd)
         End = &MI;
       else if (IsLoopStart(MI))
         Start = &MI;
-      else if (MI.getDesc().isCall())
+      else if (MI.getDesc().isCall()) {
         // TODO: Though the call will require LE to execute again, does this
         // mean we should revert? Always executing LE hopefully should be
         // faster than performing a sub,cmp,br or even subs,br.
         Revert = true;
+        LLVM_DEBUG(dbgs() << "ARM Loops: Found call.\n");
+      }
 
       if (!Dec || End)
         continue;
 
       // If we find that LR has been written or read between LoopDec and
       // LoopEnd, expect that the decremented value is being used else where.
       // Because this value isn't actually going to be produced until the
       // latch, by LE, we would need to generate a real sub. The value is also
bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
   if (Start->getOpcode() == ARM::t2WhileLoopStart &&
       (BBUtils->getOffsetOf(Start) >
        BBUtils->getOffsetOf(Start->getOperand(1).getMBB()) ||
        !BBUtils->isBBInRange(Start, Start->getOperand(1).getMBB(), 4094))) {
     LLVM_DEBUG(dbgs() << "ARM Loops: WLS offset is out-of-range!\n");
     Revert = true;
   }
 
-  Expand(ML, Start, Dec, End, Revert);
+  MachineInstr *InsertPt = Revert ? nullptr : IsSafeToDefineLR(Start);
+  if (!InsertPt) {
+    LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n");
+    Revert = true;
+  } else
+    LLVM_DEBUG(dbgs() << "ARM Loops: Start insertion point: " << *InsertPt);
+
+  Expand(ML, Start, InsertPt, Dec, End, Revert);
   return true;
 }
 
 // WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
 // beq that branches to the exit branch.
 // FIXME: Need to check that we're not trashing the CPSR when generating the
 // cmp. We could also try to generate a cbz if the value in LR is also in
 // another low register.
void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
   MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::NE);        // condition code
   MIB.addReg(ARM::CPSR);
   MI->eraseFromParent();
 }
 
 void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
+                                 MachineInstr *InsertPt,
                                  MachineInstr *Dec, MachineInstr *End,
                                  bool Revert) {
 
-  auto ExpandLoopStart = [this](MachineLoop *ML, MachineInstr *Start) {
-    // The trip count should already been held in LR since the instructions
-    // within the loop can only read and write to LR. So, there should be a
-    // mov to setup the count. WLS/DLS perform this move, so find the original
-    // and delete it - inserting WLS/DLS in its place.
-    MachineBasicBlock *MBB = Start->getParent();
-    MachineInstr *InsertPt = Start;
-    for (auto &I : MRI->def_instructions(ARM::LR)) {
-      if (I.getParent() != MBB)
-        continue;
-
-      // Always execute.
-      if (!I.getOperand(2).isImm() || I.getOperand(2).getImm() != ARMCC::AL)
-        continue;
-
-      // Only handle move reg, if the trip count it will need moving into a reg
-      // before the setup instruction anyway.
-      if (!I.getDesc().isMoveReg() ||
-          !I.getOperand(1).isIdenticalTo(Start->getOperand(0)))
-        continue;
-      InsertPt = &I;
-      break;
-    }
-
+  auto ExpandLoopStart = [this](MachineLoop *ML, MachineInstr *Start,
+                                MachineInstr *InsertPt) {
+    MachineBasicBlock *MBB = InsertPt->getParent();
     unsigned Opc = Start->getOpcode() == ARM::t2DoLoopStart ?
       ARM::t2DLS : ARM::t2WLS;
     MachineInstrBuilder MIB =
       BuildMI(*MBB, InsertPt, InsertPt->getDebugLoc(), TII->get(Opc));
 
     MIB.addDef(ARM::LR);
     MIB.add(Start->getOperand(0));
     if (Opc == ARM::t2WLS)
void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
   if (Revert) {
     if (Start->getOpcode() == ARM::t2WhileLoopStart)
       RevertWhile(Start);
     else
       Start->eraseFromParent();
     RevertLoopDec(Dec);
     RevertLoopEnd(End);
   } else {
-    Start = ExpandLoopStart(ML, Start);
+    Start = ExpandLoopStart(ML, Start, InsertPt);
     RemoveDeadBranch(Start);
     End = ExpandLoopEnd(ML, Dec, End);
     RemoveDeadBranch(End);
   }
 }
 
-bool ARMLowOverheadLoops::RevertNonLoops(MachineFunction &MF) {
+bool ARMLowOverheadLoops::RevertNonLoops() {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n");
   bool Changed = false;
 
-  for (auto &MBB : MF) {
+  for (auto &MBB : *MF) {
     SmallVector<MachineInstr*, 4> Starts;
     SmallVector<MachineInstr*, 4> Decs;
     SmallVector<MachineInstr*, 4> Ends;
 
     for (auto &I : MBB) {
       if (IsLoopStart(I))
         Starts.push_back(&I);
       else if (I.getOpcode() == ARM::t2LoopDec)

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 # CHECK-NOT: $lr = tMOVr $r0, 13
 # CHECK: $lr = t2DLS killed $r0
 # CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
 
 --- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
   entry:
     %scevgep = getelementptr i32, i32* %q, i32 -1
     %scevgep3 = getelementptr i32, i32* %p, i32 -1
     call void @llvm.set.loop.iterations.i32(i32 %n)
     br label %while.body
   
   while.body:                                       ; preds = %while.body, %entry
     %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
     %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
     %0 = phi i32 [ %n, %entry ], [ %2, %while.body ]
-    %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
-    %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
-    %1 = load i32, i32* %scevgep7, align 4
-    store i32 %1, i32* %scevgep4, align 4
+    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %1 = load i32, i32* %scevgep6, align 4
+    store i32 %1, i32* %scevgep2, align 4
     %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
     %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
     %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
     %3 = icmp ne i32 %2, 0
     br i1 %3, label %while.body, label %while.end
   
   while.end:                                        ; preds = %while.body
     ret i32 0

 ---
 name:            do_copy
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     $lr = tMOVr $r0, 14, $noreg
     t2DoLoopStart killed $r0
     renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
     renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
   
   bb.1.while.body:
     successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+    liveins: $lr, $r0, $r1
   
-    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
-    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
+    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
     tB %bb.2, 14, $noreg
   
   bb.2.while.end:
     $r0, dead $cpsr = tMOVi8 0, 14, $noreg
     tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
 
 ...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 
 # CHECK-NOT: DoLoopStart
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
 # CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
 # CHECK:   t2Bcc %bb.3, 1, $cpsr
 # CHECK:   tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
 # CHECK: bb.3.for.header:
 
---- |  
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
   entry:
     call void @llvm.set.loop.iterations.i32(i32 %N)
     %scevgep = getelementptr i32, i32* %a, i32 -1
     %scevgep4 = getelementptr i32, i32* %c, i32 -1
     %scevgep8 = getelementptr i32, i32* %b, i32 -1
     br label %for.header
   
for.header:                                       ; preds = %for.body, %entry
     %lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ]
     %lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ]
     %lsr.iv1 = phi i32* [ %scevgep, %entry ], [ %scevgep2, %for.body ]
     %count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
     br label %for.body
   }
   
   ; Function Attrs: nounwind
-  declare i32 @llvm.arm.space(i32 immarg, i32) #0 
+  declare i32 @llvm.arm.space(i32 immarg, i32) #0
+  
   ; Function Attrs: noduplicate nounwind
-  declare void @llvm.set.loop.iterations.i32(i32) #1 
+  declare void @llvm.set.loop.iterations.i32(i32) #1
+  
   ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
   
   attributes #0 = { nounwind }
   attributes #1 = { noduplicate nounwind }
 
 ...
 ---
 name:            size_limit
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
   - { reg: '$r3', virtual-reg: '' }
 frameInfo:
- { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.3(0x80000000)
+    liveins: $r0, $r1, $r2, $r3, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     $sp = frame-setup tSUBspi $sp, 8, 14, $noreg
     frame-setup CFI_INSTRUCTION def_cfa_offset 40
     t2DoLoopStart renamable $r3
bb.3.for.header:
     $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
     tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7)
     tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6)
     tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5)
     tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4)
     tB %bb.1, 14, $noreg
 
 ...
-
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir

+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
+# CHECK: $lr = t2DLS $r0
+# CHECK-NOT: $lr = tMOVr $r0
+# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
+  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+  entry:
+    %scevgep = getelementptr i32, i32* %q, i32 -1
+    %scevgep3 = getelementptr i32, i32* %p, i32 -1
+    call void @llvm.set.loop.iterations.i32(i32 %n)
+    br label %while.body
+  
+  while.body:                                       ; preds = %while.body, %entry
+    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
+    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
+    %0 = phi i32 [ %n, %entry ], [ %2, %while.body ]
+    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %1 = load i32, i32* %scevgep6, align 4
+    store i32 %1, i32* %scevgep2, align 4
+    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
+    %3 = icmp ne i32 %2, 0
+    br i1 %3, label %while.body, label %while.end
+  
+  while.end:                                        ; preds = %while.body
+    ret i32 0
+  }
+  
+  declare void @llvm.set.loop.iterations.i32(i32) #0
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+  
+  attributes #0 = { noduplicate nounwind }
+  attributes #1 = { nounwind }
+
+...
+---
+name:            do_copy
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
+  
+    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    t2DoLoopStart $r0
+    $lr = tMOVr killed $r0, 14, $noreg
+    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+  
+  bb.1.while.body:
+    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+    liveins: $lr, $r0, $r1
+  
+    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
+    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
+    tB %bb.2, 14, $noreg
+  
+  bb.2.while.end:
+    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir

 # RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
 
 # CHECK: while.body:
 # CHECK-NOT: t2DLS
 # CHECK-NOT: t2LEUpdate
 
 --- |
-  ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll'
-  source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define i32 @skip_spill(i32 %n) #0 {
   entry:
     %cmp6 = icmp eq i32 %n, 0
     br i1 %cmp6, label %while.end, label %while.body.preheader
   
--- |
   
   while.end:                                        ; preds = %while.body, %entry
     %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
     ret i32 %res.0.lcssa
   }
   
   declare i32 @bar(...) local_unnamed_addr #0
   
-  ; Function Attrs: noduplicate nounwind
   declare void @llvm.set.loop.iterations.i32(i32) #1
-  
-  ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
   
-  ; Function Attrs: nounwind
-  declare void @llvm.stackprotector(i8*, i8**) #2
-  
   attributes #0 = { "target-features"="+mve.fp" }
   attributes #1 = { noduplicate nounwind }
   attributes #2 = { nounwind }
 
 ...
 ---
 name:            skip_spill
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.4(0x30000000), %bb.1(0x50000000)
+    liveins: $r0, $r4, $r5, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 16
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     frame-setup CFI_INSTRUCTION offset $r5, -12
     frame-setup CFI_INSTRUCTION offset $r4, -16
     tCBZ $r0, %bb.4
   
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
+    liveins: $r0
   
     $lr = tMOVr $r0, 14, $noreg
     renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
     t2DoLoopStart killed $r0
   
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r4
   
     $r5 = tMOVr killed $lr, 14, $noreg
     tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
     $lr = tMOVr killed $r5, 14, $noreg
     renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
   
   bb.3.while.end:
+    liveins: $r4
+  
     $r0 = tMOVr killed $r4, 14, $noreg
     tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
   
   bb.4:
     renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
     $r0 = tMOVr killed $r4, 14, $noreg
     tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
 
 ...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir

 # RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
 
 # CHECK: while.body:
 # CHECK-NOT: t2DLS
 # CHECK-NOT: t2LEUpdate
 
---- |  
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define i32 @mov_between_dec_end(i32 %n) #0 {
   entry:
     %cmp6 = icmp eq i32 %n, 0
     br i1 %cmp6, label %while.end, label %while.body.preheader
   
   while.body.preheader:                             ; preds = %entry
     call void @llvm.set.loop.iterations.i32(i32 %n)
     br label %while.body
   
   while.body:                                       ; preds = %while.body, %while.body.preheader
-    %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
     %0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]
     %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
     %add = add i32 %1, 0
     %2 = icmp ne i32 %1, 0
     br i1 %2, label %while.body, label %while.end
   
   while.end:                                        ; preds = %while.body, %entry
     %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
     ret i32 %res.0.lcssa
   }
   
-  ; Function Attrs: noduplicate nounwind
   declare void @llvm.set.loop.iterations.i32(i32) #1
-  
-  ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
   
   attributes #0 = { "target-features"="+mve.fp" }
   attributes #1 = { noduplicate nounwind }
   attributes #2 = { nounwind }
 
 ...
 ---
 name:            mov_between_dec_end
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
-  stackSize:       16
+  stackSize:       8
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    true
-  hasCalls:        true
+  adjustsStack:    false
+  hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   cvBytesOfCalleeSavedRegisters: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
       stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.4(0x30000000), %bb.1(0x50000000)
+    liveins: $r0, $r7, $lr
   
-    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
-    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
-    frame-setup CFI_INSTRUCTION offset $r5, -12
-    frame-setup CFI_INSTRUCTION offset $r4, -16
     tCBZ $r0, %bb.4
   
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
+    liveins: $r0
   
     $lr = tMOVr $r0, 14, $noreg
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
     t2DoLoopStart killed $r0
   
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r4
   
-    renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
+    renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r4, 14, $noreg
     renamable $lr = t2LoopDec killed renamable $lr, 1
     renamable $r4 = tMOVr $lr, 14, $noreg
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
   
   bb.3.while.end:
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
+    liveins: $lr
+  
+    $r0 = tMOVr killed $lr, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
   
   bb.4:
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
+    renamable $lr = t2MOVi 0, 14, $noreg, $noreg
+    $r0 = tMOVr killed $lr, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
 
 ...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir

-# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
-
-# CHECK: while.body:
-# CHECK-NOT: t2DLS
-# CHECK-NOT: t2LEUpdate
-
---- |  
-  define i32 @skip_spill(i32 %n) #0 {
-  entry:
-    %cmp6 = icmp eq i32 %n, 0
-    br i1 %cmp6, label %while.end, label %while.body.preheader
-  
-  while.body.preheader:                             ; preds = %entry
-    call void @llvm.set.loop.iterations.i32(i32 %n)
-    br label %while.body
-  
-  while.body:                                       ; preds = %while.body, %while.body.preheader
-    %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
-    %0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]
-    %call = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)()
-    %add = add nsw i32 %call, %res.07
-    %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
-    %2 = icmp ne i32 %1, 0
-    br i1 %2, label %while.body, label %while.end
-  
-  while.end:                                        ; preds = %while.body, %entry
-    %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
-    ret i32 %res.0.lcssa
-  }
-  
-  declare i32 @bar(...) local_unnamed_addr #0
-  
-  ; Function Attrs: noduplicate nounwind
-  declare void @llvm.set.loop.iterations.i32(i32) #1
-  
-  ; Function Attrs: noduplicate nounwind
-  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
-  
-  ; Function Attrs: nounwind
-  declare void @llvm.stackprotector(i8*, i8**) #2
-  
-  attributes #0 = { "target-features"="+mve.fp" }
-  attributes #1 = { noduplicate nounwind }
-  attributes #2 = { nounwind }
-
-...
----
-name:            skip_spill
-alignment:       2
-exposesReturnsTwice: false
-legalized:       false
-regBankSelected: false
-selected:        false
-failedISel:      false
-tracksRegLiveness: false
-hasWinCFI:       false
-registers:       []
-liveins:
-  - { reg: '$r0', virtual-reg: '' }
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       16
-  offsetAdjustment: 0
-  maxAlignment:    4
-  adjustsStack:    true
-  hasCalls:        true
-  stackProtector:  ''
-  maxCallFrameSize: 0
-  cvBytesOfCalleeSavedRegisters: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-  localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
-fixedStack:      []
-stack:
-  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-callSites:       []
-constants:       []
-machineFunctionInfo: {}
-body:             |
-  bb.0.entry:
-    successors: %bb.4(0x30000000), %bb.1(0x50000000)
-  
-    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
-    frame-setup CFI_INSTRUCTION def_cfa_offset 16
-    frame-setup CFI_INSTRUCTION offset $lr, -4
-    frame-setup CFI_INSTRUCTION offset $r7, -8
-    frame-setup CFI_INSTRUCTION offset $r5, -12
-    frame-setup CFI_INSTRUCTION offset $r4, -16
-    tCBZ $r0, %bb.4
-  
-  bb.1.while.body.preheader:
-    successors: %bb.2(0x80000000)
-  
-    $lr = tMOVr $r0, 14, $noreg
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
-    t2DoLoopStart killed $r0
-  
-  bb.2.while.body:
-    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
-  
-    $r5 = tMOVr killed $lr, 14, $noreg
-    tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
-    $lr = tMOVr killed $r5, 14, $noreg
-    renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
-    renamable $lr = t2LoopDec killed renamable $lr, 1
-    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
-    tB %bb.3, 14, $noreg
-  
-  bb.3.while.end:
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
-  
-  bb.4:
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
-
-...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir

 # RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
 
 # CHECK: while.body:
 # CHECK-NOT: t2DLS
 # CHECK-NOT: t2LEUpdate
 
---- |  
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define i32 @mov_between_dec_end(i32 %n) #0 {
   entry:
     %cmp6 = icmp eq i32 %n, 0
     br i1 %cmp6, label %while.end, label %while.body.preheader
   
   while.body.preheader:                             ; preds = %entry
     call void @llvm.set.loop.iterations.i32(i32 %n)
     br label %while.body
   
   while.body:                                       ; preds = %while.body, %while.body.preheader
-    %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
     %0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]
     %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
     %add = add i32 %1, 2
     %2 = icmp ne i32 %1, 0
     br i1 %2, label %while.body, label %while.end
   
   while.end:                                        ; preds = %while.body, %entry
     %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
     ret i32 %res.0.lcssa
   }
   
   ; Function Attrs: noduplicate nounwind
   declare void @llvm.set.loop.iterations.i32(i32) #1
   
   ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
   
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #2
+  
   attributes #0 = { "target-features"="+mve.fp" }
   attributes #1 = { noduplicate nounwind }
   attributes #2 = { nounwind }
 
 ...
 ---
 name:            mov_between_dec_end
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
-  stackSize:       16
+  stackSize:       8
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    true
-  hasCalls:        true
+  adjustsStack:    false
+  hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   cvBytesOfCalleeSavedRegisters: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
       stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 
-      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.4(0x30000000), %bb.1(0x50000000)
+    liveins: $r0, $r7, $lr
   
-    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
-    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
-    frame-setup CFI_INSTRUCTION offset $r5, -12
-    frame-setup CFI_INSTRUCTION offset $r4, -16
     tCBZ $r0, %bb.4
   
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
+    liveins: $r0
   
     $lr = tMOVr $r0, 14, $noreg
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
     t2DoLoopStart killed $r0
   
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr
   
     $r4 = tMOVr $lr, 14, $noreg
     renamable $lr = t2LoopDec killed renamable $lr, 1
+    renamable $r0 = t2ADDri renamable $lr, 2, 14, $noreg, $noreg
     $lr = tMOVr $r4, 14, $noreg
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
   
   bb.3.while.end:
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
+    liveins: $r0
+  
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
   
   bb.4:
-    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
-    $r0 = tMOVr killed $r4, 14, $noreg
-    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
+    renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
 
 ...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s
 
 # CHECK: name: non_loop
 # CHECK: bb.0.entry:
 # CHECK:   tBcc %bb.2, 3
 # CHECK: bb.1.not.preheader:
 # CHECK:   t2CMPri renamable $lr, 0, 14
 # CHECK:   t2Bcc %bb.4, 0
 # CHECK:   tB %bb.2
 # CHECK: bb.3.while.body:
 # CHECK:   t2CMPri $lr, 0, 14
 # CHECK:   t2Bcc %bb.3, 1
 # CHECK:   tB %bb.4
 # CHECK: bb.4.while.end:
 
 --- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
   entry:
     %cmp = icmp ugt i32 %N, 2
     br i1 %cmp, label %not.preheader, label %while.body.preheader
   
   not.preheader:                                    ; preds = %entry
     %test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
     br i1 %test, label %while.body.preheader, label %while.end
   
-  while.body.preheader:                             ; preds = %entry, %not.preheader
+  while.body.preheader:                             ; preds = %not.preheader, %entry
     %scevgep = getelementptr i16, i16* %a, i32 -1
     %scevgep3 = getelementptr i16, i16* %b, i32 -1
     br label %while.body
   
-  while.body:                                       ; preds = %while.body.preheader, %while.body
+  while.body:                                       ; preds = %while.body, %while.body.preheader
     %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
     %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
     %count = phi i32 [ %count.next, %while.body ], [ %N, %while.body.preheader ]
-    %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1
-    %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1
-    %load = load i16, i16* %scevgep6, align 2
-    store i16 %load, i16* %scevgep2, align 2
+    %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
+    %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
+    %load = load i16, i16* %scevgep4, align 2
+    store i16 %load, i16* %scevgep7, align 2
     %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
     %cmp1 = icmp ne i32 %count.next, 0
     %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
     %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
     br i1 %cmp1, label %while.body, label %while.end
   
   while.end:                                        ; preds = %while.body, %not.preheader
     ret void
   }
   
-  ; Function Attrs: noduplicate nounwind
   declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
-  
-  ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
-  
-  ; Function Attrs: nounwind
   declare void @llvm.stackprotector(i8*, i8**) #1
   
   attributes #0 = { noduplicate nounwind }
   attributes #1 = { nounwind }
 
 ...
 ---
 name:            non_loop
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     $lr = tMOVr $r2, 14, $noreg
     tCMPi8 killed $r2, 3, 14, $noreg, implicit-def $cpsr
     tBcc %bb.2, 3, killed $cpsr
   
   bb.1.not.preheader:
     successors: %bb.2(0x40000000), %bb.4(0x40000000)
+    liveins: $lr, $r0, $r1
   
     t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr
     tB %bb.2, 14, $noreg
   
   bb.2.while.body.preheader:
     successors: %bb.3(0x80000000)
+    liveins: $lr, $r0, $r1
   
     renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
     renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
   
   bb.3.while.body:
     successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+    liveins: $lr, $r0, $r1
   
-    renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6)
-    early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2)
+    renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
+    early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
     tB %bb.4, 14, $noreg
   
   bb.4.while.end:
     tPOP_RET 14, $noreg, def $r7, def $pc
 
 ...

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK:      body:
 # CHECK:      bb.0.entry:
 # CHECK:        t2CMPri $r3, 0, 14
 # CHECK-NEXT:   t2Bcc %bb.3, 0, $cpsr
 # CHECK-NEXT:   tB %bb.1
 # CHECK:      bb.1.do.body.preheader:
 # CHECK:        $lr = tMOVr killed $r3
 # CHECK:      bb.2.do.body:
 # CHECK:        $lr = t2SUBri killed renamable $lr, 1, 14
 # CHECK-NEXT:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
 # CHECK-NEXT:   t2Bcc %bb.2, 1, $cpsr
 # CHECK-NEXT:   tB %bb.3, 14
 
 --- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
   define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 {
   entry:
     %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
     br i1 %0, label %do.body.preheader, label %if.end
   
   do.body.preheader:                                ; preds = %entry
     %scevgep2 = getelementptr i32, i32* %a, i32 -1
     %scevgep5 = getelementptr i32, i32* %b, i32 -1
     br label %do.body
   
-  do.body:                                          ; preds = %do.body.preheader, %do.body
+  do.body:                                          ; preds = %do.body, %do.body.preheader
     %lsr.iv6 = phi i32* [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ]
     %lsr.iv = phi i32* [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ]
     %1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ]
-    %scevgep8 = getelementptr i32, i32* %lsr.iv6, i32 1
-    %scevgep4 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep = getelementptr i32, i32* %lsr.iv6, i32 1
+    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
     %size = call i32 @llvm.arm.space(i32 4096, i32 undef)
-    %tmp = load i32, i32* %scevgep8, align 4
-    store i32 %tmp, i32* %scevgep4, align 4
+    %tmp = load i32, i32* %scevgep, align 4
+    store i32 %tmp, i32* %scevgep1, align 4
     %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
     %3 = icmp ne i32 %2, 0
     %scevgep3 = getelementptr i32, i32* %lsr.iv, i32 1
     %scevgep7 = getelementptr i32, i32* %lsr.iv6, i32 1
     br i1 %3, label %do.body, label %if.end
   
   if.end:                                           ; preds = %do.body, %entry
     ret void
   }
   
   ; Function Attrs: nounwind
   declare i32 @llvm.arm.space(i32 immarg, i32) #1
   
   ; Function Attrs: noduplicate nounwind
   declare i1 @llvm.test.set.loop.iterations.i32(i32) #2
   
   ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
   
-  ; Function Attrs: nounwind
-  declare void @llvm.stackprotector(i8*, i8**) #1
-  
   attributes #0 = { "target-features"="+lob" }
   attributes #1 = { nounwind }
   attributes #2 = { noduplicate nounwind }
 
 ...
 ---
 name:            ne_trip_count
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
   - { reg: '$r3', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.3(0x40000000)
+    liveins: $r1, $r2, $r3, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2WhileLoopStart $r3, %bb.3, implicit-def dead $cpsr
     tB %bb.1, 14, $noreg
   
   bb.1.do.body.preheader:
     successors: %bb.2(0x80000000)
+    liveins: $r1, $r2, $r3
   
     renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
     renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
     $lr = tMOVr killed $r3, 14, $noreg
   
   bb.2.do.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r0, $r1
   
     dead renamable $r2 = SPACE 4096, undef renamable $r0
-    renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep8)
-    early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+    renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep)
+    early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
   
   bb.3.if.end:
     tPOP_RET 14, $noreg, def $r7, def $pc
 
 ...
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir

+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
+# CHECK: $lr = t2DLS $r0
+# CHECK: $lr = tMOVr $r0, 14
+# CHECK: $lr = t2LEUpdate renamable $lr, %bb.2
+
+# TODO: Explore the preheader to remove the redundant tMOVr
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
+  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+  entry:
+    %scevgep = getelementptr i32, i32* %q, i32 -1
+    %scevgep3 = getelementptr i32, i32* %p, i32 -1
+    call void @llvm.set.loop.iterations.i32(i32 %n)
+    br label %preheader
+
+  preheader:
+    br label %while.body
+  
+  while.body:                                       ; preds = %while.body, %entry
+    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]
+    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]
+    %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]
+    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %1 = load i32, i32* %scevgep6, align 4
+    store i32 %1, i32* %scevgep2, align 4
+    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
+    %3 = icmp ne i32 %2, 0
+    br i1 %3, label %while.body, label %while.end
+  
+  while.end:                                        ; preds = %while.body
+    ret i32 0
+  }
+  
+  declare void @llvm.set.loop.iterations.i32(i32) #0
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+  
+  attributes #0 = { noduplicate nounwind }
+  attributes #1 = { nounwind }
+
+...
+---
+name:            do_copy
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
+  
+    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    t2DoLoopStart $r0
+    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+
+  bb.1.preheader:
+    successors: %bb.2(0x80000000)
+    liveins: $r0
+    $lr = tMOVr $r0, 14, $noreg
+  
+  bb.2.while.body:
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r0, $r1
+  
+    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
+    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+    tB %bb.3, 14, $noreg
+  
+  bb.3.while.end:
+    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir

+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
+# CHECK-NOT: $lr = t2DLS
+# CHECK: $lr = tMOVr $r0, 14
+# CHECK-NOT: $lr = t2LEUpdate
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
+  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+  entry:
+    %scevgep = getelementptr i32, i32* %q, i32 -1
+    %scevgep3 = getelementptr i32, i32* %p, i32 -1
+    call void @llvm.set.loop.iterations.i32(i32 %n)
+    br label %preheader
+
+  preheader:
+    br label %while.body
+  
+  while.body:                                       ; preds = %while.body, %entry
+    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]
+    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]
+    %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]
+    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %1 = load i32, i32* %scevgep6, align 4
+    store i32 %1, i32* %scevgep2, align 4
+    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
+    %3 = icmp ne i32 %2, 0
+    br i1 %3, label %while.body, label %while.end
+  
+  while.end:                                        ; preds = %while.body
+    ret i32 0
+  }
+  
+  declare void @llvm.set.loop.iterations.i32(i32) #0
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+  
+  attributes #0 = { noduplicate nounwind }
+  attributes #1 = { nounwind }
+
+...
+---
+name:            do_copy
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
+  
+    frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    t2DoLoopStart $r0
+    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+
+  bb.1.preheader:
+    successors: %bb.2(0x80000000)
+    liveins: $r0, $lr
+    $lr = tMOVr $r0, 14, $noreg
+  
+  bb.2.while.body:
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r0, $r1
+  
+    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
+    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+    tB %bb.3, 14, $noreg
+  
+  bb.3.while.end:
+    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir

+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
+# CHECK-NOT: $lr = t2DLS
+# CHECK: $lr = tMOVr $r0, 14
+# CHECK-NOT: $lr = t2LEUpdate
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main"
+  
+  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+  entry:
+    %scevgep = getelementptr i32, i32* %q, i32 -1
+    %scevgep3 = getelementptr i32, i32* %p, i32 -1
+    call void @llvm.set.loop.iterations.i32(i32 %n)
+    br label %preheader
+
+  preheader:
+    br label %while.body
+  
+  while.body:                                       ; preds = %while.body, %entry
+    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]
+    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]
+    %0 = phi i32 [ %n, %preheader ], [ %2, %while.body ]
+    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %1 = load i32, i32* %scevgep6, align 4
+    store i32 %1, i32* %scevgep2, align 4
+    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
+    %3 = icmp ne i32 %2, 0
+    br i1 %3, label %while.body, label %while.end
+  
+  while.end:                                        ; preds = %while.body
+    ret i32 0
+  }
+  
+  declare void @llvm.set.loop.iterations.i32(i32) #0
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+  
+  attributes #0 = { noduplicate nounwind }
+  attributes #1 = { nounwind }
+
+...
+---
+name:            do_copy
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
+  
+    frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    t2DoLoopStart $r0
+    renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def $cpsr
+    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+
+  bb.1.preheader:
+    successors: %bb.2(0x80000000)
+    liveins: $r0
+    $lr = tMOVr $r0, 14, $noreg
+  
+  bb.2.while.body:
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r0, $r1
+  
+    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
+    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+    tB %bb.3, 14, $noreg
+  
+  bb.3.while.end:
+    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir

 # RUN: llc -O0 -run-pass=arm-low-overhead-loops -o - -verify-machineinstrs %s | FileCheck %s
 # CHECK-NOT: WLS
 # CHECK-NOT: WhileLoopStart
 
 --- |
-  ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.ll'
-  source_filename = "while-size-limit.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) #0 {
   entry:
     br label %while
   
   for.cond.cleanup:                                 ; preds = %while, %for.body
--- |
   
   while:                                            ; preds = %entry
     %cmp8 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
     br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup
   }
   
   ; Function Attrs: nounwind
   declare i32 @llvm.arm.space(i32 immarg, i32) #1
+  
   ; Function Attrs: noduplicate nounwind
   declare i1 @llvm.test.set.loop.iterations.i32(i32) #2
+  
   ; Function Attrs: noduplicate nounwind
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
   
   attributes #0 = { "target-features"="+lob" }
   attributes #1 = { nounwind }
   attributes #2 = { noduplicate nounwind }
 
 ...
 ---
 name:            size_limit
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
   - { reg: '$r3', virtual-reg: '' }
 frameInfo:
- { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.4(0x80000000)
+    liveins: $r0, $r1, $r2, $r3, $r4, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r4, -8
     $sp = frame-setup tSUBspi $sp, 8, 14, $noreg
     frame-setup CFI_INSTRUCTION def_cfa_offset 40
     tSTRspi killed $r3, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
body:             |
   bb.4.while:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
   
     $r0 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
     t2WhileLoopStart killed renamable $r0, %bb.1, implicit-def dead $cpsr
     tB %bb.2, 14, $noreg
 
 ...
-
-

llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
 
 # TODO: Remove the lr = tMOVr
 # CHECK: body:
 # CHECK: entry:
 # CHECK:   $lr = t2WLS $r2, [[EXIT:%bb[.0-9]+]]
 # CHECK: [[PREHEADER:bb[.0-9a-z]+]]:
 # CHECK:   $lr = tMOVr killed $r2
 # CHECK: [[BODY:bb[.0-9a-z]+]]:
 # CHECK:   $lr = t2LEUpdate renamable $lr
 
 --- |
-  ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll'
-  source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define dso_local arm_aapcscc void @copy(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
   entry:
     %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
     br i1 %0, label %while.body.preheader, label %while.end
   
   while.body.preheader:                             ; preds = %entry
     %scevgep = getelementptr i16, i16* %a, i32 -1
     %scevgep3 = getelementptr i16, i16* %b, i32 -1
     br label %while.body
   
-  while.body:                                       ; preds = %while.body.preheader, %while.body
+  while.body:                                       ; preds = %while.body, %while.body.preheader
     %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
     %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
     %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]
-    %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1
-    %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1
-    %2 = load i16, i16* %scevgep6, align 2, !tbaa !2
-    store i16 %2, i16* %scevgep2, align 2, !tbaa !2
+    %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
+    %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
+    %2 = load i16, i16* %scevgep4, align 2
+    store i16 %2, i16* %scevgep7, align 2
     %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
     %4 = icmp ne i32 %3, 0
     %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
     %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
     br i1 %4, label %while.body, label %while.end
   
   while.end:                                        ; preds = %while.body, %entry
     ret void
   }
   
   declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
   
   attributes #0 = { noduplicate nounwind }
   attributes #1 = { nounwind }
-  
-  !llvm.module.flags = !{!0, !1}
-  
-  !0 = !{i32 1, !"wchar_size", i32 4}
-  !1 = !{i32 1, !"min_enum_size", i32 4}
-  !2 = !{!3, !3, i64 0}
-  !3 = !{!"short", !4, i64 0}
-  !4 = !{!"omnipotent char", !5, i64 0}
-  !5 = !{!"Simple C/C++ TBAA"}
-
 ...
 ---
 name:            copy
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
-tracksRegLiveness: false
+tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.3(0x40000000)
+    liveins: $r0, $r1, $r2, $r7, $lr
   
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2WhileLoopStart $r2, %bb.3, implicit-def dead $cpsr
     tB %bb.1, 14, $noreg
   
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
+    liveins: $r0, $r1, $r2
   
     renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
     renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
     $lr = tMOVr killed $r2, 14, $noreg
   
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r0, $r1
   
-    renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6, !tbaa !2)
-    early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2, !tbaa !2)
+    renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
+    early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
   
   bb.3.while.end:
     tPOP_RET 14, $noreg, def $r7, def $pc
 
 ...
-